# Resetting reset to zero after one clock cycle in verilog

I'm having trouble setting the Start(reset) to zero after being high for one clock edge. I've searched online and tried different ways of writing the clock, but what is puzzling to me is that when I set Start as 1, the clock does not toggle like it should. It is as if Start being high is blocking the execution of the clock code. Here it is:

initial begin
Clock = 0;
Start = 1'b1;
forever begin
#20 Clock = ~Clock;
end
end

initial begin
@(negedge Clock);
Start = 1'b0;
@(negedge Start);
X = 3'd5;
end


My output waveform will look like that this:

Then, if I set the code to be as such:

initial begin
Clock = 0;
Start = 1'b1;
#20
Start = 1'b0;
forever begin
#20 Clock = ~Clock;
end
end

initial begin
@(negedge Start);
X = 3'd5;
end


I'll get the output waveform in the pic below. I don't want that though. I want the clock to be doing its normal pulses independently of Start changing. How do I achieve that?

• You have two initial blocks. Nov 14, 2017 at 15:20
• I only see one picture. Nov 14, 2017 at 15:36
• Sorry, I didn't know how to include both pictures in the post. One was just in a link under the number 2 but it is edited now. Nov 14, 2017 at 18:38

## 1 Answer

I'm guessing you are trying to do something like below. Note the #1 for guarding against the negedge Clock from x to 0 at time 0.

initial begin
Clock = 1'b0;
forever begin
#20 Clock = ~Clock;
end
end

initial begin
Start = 1'b1;
#1; // little delay so x->0 transition does not trigger negedge Clock
@(negedge Clock);
Start = 1'b0;
// @(negedge Start); // not needed as we know Start fell
X = 3'd5;
end

• Hi, thanks for your answer. It seems that after running synthesis my test bench worked just fine. But thanks anyway! What's the difference between running synthesis and behavioral simulation? Nov 14, 2017 at 18:37
• You don't normally synthesize a test-bench. Most test-benches use non-synthesizable code; ex: # delays, wait statements, while loops, forever blocks, fork-join, etc. Synthesizable code is a subset of features and specific coding styles compared to the score of everything available in Verilog.
– Greg
Nov 14, 2017 at 18:51
• Oh I didn't synthesize the test-bench. I synthesized my verilog module. And somehow that helped resolve the clocking issue Nov 14, 2017 at 19:00