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i am trying to implement an MIPS processor in Vivado ysing Vhdl.i have already written code for processor that has register file ,memory and all other functional units. Now I am trying to create a test bench and i want to understand the concept of writing the testbench in HDL languages.

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    \$\begingroup\$ I would suggest you to familiarize yourself with testbenches on design (much) simpler than MIPS processor. Actually I don't even believe one can design such a processor without knowing the concept of testbenches. \$\endgroup\$
    – Eugene Sh.
    Nov 14, 2017 at 18:57
  • \$\begingroup\$ I would suggest you to go to the doctor and have your eyes checked. Because if you think an image looks correct like that, then you got 90-degrees-syndrome. 100% of worlds population don't have that syndrome. \$\endgroup\$ Nov 14, 2017 at 19:20

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A test bench is a mean of automatically generating test-vectors, to test your design and make sure that the functionality is met. Without a test bench you will have to manually force all possible input combinations and verify all the outputs in simulation waveform, which is a tedious task.

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