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I am designing a system that incorporates an FPGA, a few ADCs, and a few DACs. I am curious as to what my best options may be for grounding in my system.

The FPGA is on its own daughter board, but digital signals coming from it could be up to 25MHz. The ADCs will be clocked by this 25MHz signal. The signals going to the DACs will not be any faster than 5MHz. The DACs themselves are connected to a chain of op-amps, which are being used to generate a high-voltage (between 65V and -65V) DC signal. This DC signal will not change any faster than 500kHz.

From the research I've done, it seems that there's no One Good Way™ to connect analog and digital grounds in a sensitive circuit. That being said, I'm hoping someone with more experience than me can weigh in on what grounding technique may be the most effective for my application. Initially in my schematic, I separated analog and digital grounds and planned to follow a "fenced" design, where a long slot would separate the analog and digital ground, and they would only be connected in a few places. Some of the analog components share power rails with each other, but none of them share a power supply with the digital components.

Based on the types of signals and frequencies I'm operating at, is what I'm thinking considered overkill? Not enough? Any advice is appreciated.

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The best way is to minimize R & L of current carrying paths for each and ensure path layout does not share ground or Vcc. This includes broad spectrum and DC. This requires understanding of LdI/dt of pulse noise and stray coupling into high Z inputs by mismatched Z (sig and ground), radiated current loops and E field pF coupling of noise to signals.

If connections are lower impedance than source shared load regulation conducted noise is possible. Then low Q , LC decoupling is necessary with Agnd plane balanced inputs and small loop noise currents using Cap per IC etc.

I wonder still uses extremely thin layers between power ground planes to Z(f) of power planes. There is a business doing this specialty that started around 30 yrs ago.

Additional references:

  1. http://www.ti.com/lit/an/scaa048/scaa048.pdf
  2. http://www.analog.com/media/en/training-seminars/tutorials/MT-101.pdf
  3. https://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf
  4. http://www.ewh.ieee.org/r4/se_michigan/emcs/DL-ARCH-decoupling3.pdf
  5. https://www.xilinx.com/support/documentation/application_notes/xapp623.pdf
  6. http://ds.murata.co.jp/software/simsurfing/en-us/#app=71e3&ee37-selectedIndex=0

When looking at s21 crosstalk or s22 load regulation, we expect to have a low source Z(f) and load Z(f) <1% at DC but AC ratio can be quite different due to a complex distributed RLC network of signals. So an RF Network Analyzer is an extremely valuable learning or debugging tool.

The easy way to understand these curves for scattering (s) parameters is that Ohm's Law on a voltage divider is the same as load regulated ratio of load to source Z(f) ratio in dB. Even dynamic crosstalk and noise ingress can be seen as a transfer function.

Every application may be different and require some of the solutions avail to reduce emanations or susceptibility or both

  • CM chokes (LF or RF)
  • balanced differential lines
  • active guarding on shield or gnd between all A and D signals.
  • filtering to reduce noise bandwidth
  • high CMMR before amplification.
  • strict care on Vref shared grounds to ensure no digital current is shared.
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  • \$\begingroup\$ How can the circuit function if AGND and DGND, say on an ADC, are never connected? Don't they need to be connected somewhere? \$\endgroup\$ – Billy Kalfus Nov 14 '17 at 22:41
  • \$\begingroup\$ They must be connected somewhere close to lowest ESR cap and gnd plane but sharing A gnd with logic signals is verbotten. You must imagine the current loops and know the CdV/dt effects on I. then the inductive tracks have LdI/dt effects on V, .. Loop (mA) induced H fields and parallel V induced E fields can be modelled, and tested to grasp a thorough understanding. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 14 '17 at 22:45
  • \$\begingroup\$ try a relay NC contacts in series with coil (buzzer) and put near a scope probe , then shorted 10:1 probe with 1 turn inside or outside loop or attach to a wire for parallel pF coupling. then add 100 Ohms to probe as shunt and compare with 1M ohm or 10Mohm load to probe as a noise sniffer. See the inverse square loss of noise and spectrum then share scope gnd with relay gnd and move power ground around to see conducted noise. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 14 '17 at 22:50
  • \$\begingroup\$ Since the supplies are separate, the only places AGND and DGND would need to connect is near the ADC/DACs. Therefore any current loops in the amps/FPGA should remain on their respective planes. So, if I put the slot going under the ADC/DACs (the pinout of these chips is conducive to this), and then connect the grounds directly under them and put low-ESR caps there, do you think this would be a good way to take care of it? \$\endgroup\$ – Billy Kalfus Nov 14 '17 at 22:55
  • \$\begingroup\$ except that is the old method of thinking. A contiguous ground plane that is shared for Analogue & Digital is preferred. A consideration of the associated return currents is what is key and that relies zoning analogue and digital electronics so digital signals do not go near analogue. Separate NON-OVERLAPPING powerplanes is key though \$\endgroup\$ – JonRB Nov 14 '17 at 22:59
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I don't see a concrete answer here - I think Tony is hinting that your approach is contingent on your larger design.

That being said, it sounds like you have a mixed signal design with a lot of digital energy (The +/- 65 VDC Signals).

Personally (YMMV):

Split the two ground planes, connect them with either back to back Schottky diodes or an appropriate ferrite bead. I'd provision both and include features in the layout to adjust the (0 ohm, decoupling caps, whatever as potential no-stuffs) ground topology.

This white paper supports my recommendation and is reasonably concise and spares (most) of the theory and focus's on more practical applications:

http://www.ti.com/lit/an/slyt499/slyt499.pdf

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  • \$\begingroup\$ Good TI link. Consistent with my answer. Star distribution and separate low Q ferrite LC filters ( if shared V) with low ESR caps at ADC chip. Yes EMI must always look at the system as a whole in addition to details in the radiated and conducted dI/dt, dV/dt, with details in BOM and/or schematic on ESR,ESL, cable routing, shielding termination etc. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 15 '17 at 1:53
  • \$\begingroup\$ Part1 actually agrees with my issue with split and equally part2 supports my view of one find but managed returns \$\endgroup\$ – JonRB Nov 17 '17 at 7:36

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