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Minimum number of complementary CMOS transistors pair will be required to implement function,\$F=ABC+\overline{(A+B+C)}\$ are?

\$(A)6\$

\$(B)7\$

\$(C)8\$

\$(D)9\$


I tried like this but I am getting 7 CMOS pair but answer key says its 9 CMOS pair.whats the mistake I am doing? enter image description here

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You did it wrong by connecting the output of the first stage to the output of the second stage. The correct way would be :enter image description here

TOTAL = 4 + 3 + 2 = 9 CMOS pairs

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  • \$\begingroup\$ sir i have still one doubt please clarify what will be the output when i cascade it like that in my answer?I am just confused why thats wrong actually. \$\endgroup\$ – Rohit Nov 16 '17 at 13:14
  • \$\begingroup\$ Unpredictable/undefined if both outputs are driving different logic level at the same time. We don't do it in a circuit. \$\endgroup\$ – Mitu Raj Nov 16 '17 at 13:43
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    \$\begingroup\$ You can do like that ONLY for open collector/drain gates, where only one of the gates drives the output at a time, and other gates goes to high impedance state. Check this Wikipedia article - "Wired logic connection " \$\endgroup\$ – Mitu Raj Nov 16 '17 at 13:53
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The problem is not in the second stage, it is in the 1st stage. A+B+C shouldn't be connected in series in nmos to get required answer, it is a blunder. But the not of A B C should be connected in series.So you require 3 not gates to prepare A B C not. So Then the 2nd stage is not even required. Thank you.

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