For this particular question, I am wondering if Q1 must be in saturation mode or active? I am aware Q2 must be in saturation but upon trying to solve this circuit I feel as if I have more unknowns than equations. I would show my work but it does not make sense because I cannot straighten out my thought process. anything help would be appreciated as I feel I am missing a key fact. thanks! enter image description here


It is easiest to pull the most current from Q2b if Q1 is in saturation. Additionally, the lowest voltage drop across Q2 is when it is in saturation. Therefore you should solve this question with each transistor in saturation during the appropriate time.

  • \$\begingroup\$ What do you mean the appropriate time? my problem is that I am trying to do KLC at q1, and q2 by replacing each transistor with its active model, but I do not know the currents of the wire connected to ground or the current of the emitter for q2, I am still fairly new to mna so please forgive me if I lack some knowledge. \$\endgroup\$ – jay rivera Nov 18 '17 at 6:09

This question seems very academic and poorly written.

Both transistors must be in saturation and Vce(sat) is only value for a defined Ic/Ib ratio which is certainly not hFE and is more like from < 20% of hFE to 10:1 ratio when Vce< 1V.

Also you can't assume the source impedance of 3V logic but it is only rated for 3.3V then the out impedance is around 33 ohms or 25 Ohms at 3.3V while 5V logic is closer to 50 Ohms nom.

0.02% accurate values? with hFE being invalid during saturation. Sorry that's impossible in reality. At best there are only 2 significant figures. What are you teaching here ? How to design with significant error and insignificant figures?

Rc only shares some of the Ic1 in order to turn off Q2.

Rc2 the motor , we can assume from Ic2 = start current of 0.4A at (10.9V -Vce2)
Again Datasheets always define Vce(sat with Ic/Ib=10 and sometimes also =20,50 for devices with hFE>= 1000 where 10% to 20% of this linear beta is possible.

MOTOROLA used to call it beta overdrive factor in the 60's and 70's.

I would assume Ic2/Ib2=10 and Ic1/Ib1=10 and let I(Rc)= 10% of Ib2 then realize the 2stage current gain has to be at least 11*10 so the input current must be 400mA/110 =3.636 mA with 2.3V/3.6 mA = 825 ohms with at least 25 Ohms to 33 ohms in the CMOS driver impedance so choose 825-33 Ohms for Rb1 and go from there.


@JayRivera, the way this question is worded is somewhat bogus IMO. The beta value given in the problem statement is for forward-active mode, not for saturation. For small-signal transistors \$\beta_{sat} \approx 10\$, and this is the value I recommend you use in the equations that follow.

The way I'd approach this problem is as follows. First, I want both Q1 and Q2 to be driven into saturation because 1) saturation minimizes the power dissipated by Q1 and Q2 in their "ON" state, and 2) saturation ensures maximum power delivery through the transistor and into the load (the motor in this case).

The problem statement indicates Q2's collector saturation current is \$I_{C2(sat)}=400\,mA\$. Q2's base current must therefore be,

$$ I_{B2(sat)}=I_{C2(sat)}/\beta_{sat} \;\;\;\;\;\;\;\;(1) $$

I will design this circuit to ensure Q1 is driven into saturation (see below). Therefore, as per the problem statement, Q1's collector-emitter saturation voltage \$V_{CE1(sat)}=0.2\,V\$ and Q2's base-emitter voltage is \$V_{BE2(sat)}=-0.7\,V\$ (n.b., \$V_{EB2(sat)}=+0.7\,V\$). I now know enough information to solve for \$R_{B2}\$'s value:

$$ R_{B2}=\frac{V_{DC}-V_{EB2(sat)}-V_{CE1(sat)}}{I_{B2(sat)}} \;\;\;\;\;\;\;\;(2) \\[0.3in] =\frac{10.9\,V-0.7\,V-0.2\,V}{40\,mA} $$

The current flowing through resistor \$R_C\$ contributes to Q1's collector current, so calculate the current through \$R_C\$:

$$ I_{RC}=\frac{V_{DC}-V_{CE1(sat)}}{R_C} \;\;\;\;\;\;\;\;(3) $$

Now I have enough information to determine the current flowing into Q1's collector,

$$ I_{C1(sat)}=I_{RC}+I_{B2(sat)} \;\;\;\;\;\;\;\;(4) $$

and therefore I know how much base current I require to saturate Q1,

$$ I_{B1(sat)}=I_{C1(sat)}/\beta_{sat} \;\;\;\;\;\;\;\;(5) $$

Now I can calculate a value for \$R_{B1}\$ that ensures a current of \$I_{B1(sat)}\$ flows into \$Q1_B\$ when the microcontroller outputs a logic HIGH (ONE) voltage (see also Note 1):

$$ R_{B1}=\frac{V_{OH}-V_{BE1(sat)}}{I_{B1(sat)}} \;\;\;\;\;\;\;\;(6) $$

where \$V_{OH}\$ is the minimum voltage that represents a logic HIGH (ONE) output voltage at the microcontroller's digital output pin:

$$ V_{OH} \le V_{LogicOne} \le 3.0\,V \;\;\;\;\;\;\;\;(7) $$

Using this approach I solved for RB1 and RB2, and then I ran a PSpice simulation with Q1=2N3904 (NPN) and Q2=2N4403 (PNP). The results of that simulation (with voltage source V2 outputting 3 Volts) are shown in Figure 1.

(HINT: NPN transistors are in saturation when \$V_E \lt V_B \gt V_C\$. Likewise, PNP transistors are in saturation when \$V_E \gt V_B \lt V_C\$.)

PSpice Simulation Results (Current) Figure 1. PSpice simulation results: current values for \$V_2=3\,V\$. The PSpice simulation calculates for me the value of load resistor \$R_4\$ as \$\{10.7V/0.4A\}\,\Omega\$, where \$V_{CC}-V_{EC2(sat)}=10.7\,V\$.

PSpice Simulation Results (Voltage) Figure 1. (cont.) PSpice simulation results: voltage values for \$V_2=3\,V\$.


  1. Equation 6 does not take into account the digital output pin's output impedance \$R_{OUT}\$. In cases where the digital pin must source (or sink) a "significant" amount of current, the pin's output (or input) impedance becomes important and should be included in your \$R_{B1}\$ calculation.

$$ R_{B1}+R_{OUT}=\frac{V_{OH}-V_{BE1(sat)}}{I_{B1(sat)}} \;\;\;\;\;\;\;\;(7) $$


The equation is (keeping Q1 and Q2 both in linear):

EDIT: $$ \require{cancel} \xcancel{I_M = I_{C2} = \frac{β_F(V_{DC} - β_F R_{C}(\frac{V_{IN}}{R_{B1}}))} {R_{B2}}}$$

is now:

$$ I_M = I_{C2} = \frac{β_F^2 V_{IN} R_C}{R_{B1} (R_{B2} + 2R_C)}$$

I had it in my head that Q2 was voltage following, rather it's a current divider. So I made the mistake.


$$ I_M ≤ 0.4A \; (max \; motor \; current \; at \; V_{DC} = 10.9V)$$

For each BJT to reach saturation:


EDIT: $$ \require{cancel} \xcancel{V_{DC} < β_F R_{C1}(\frac{V_{IN}}{R_{B1}}) \; + \; V_{CE\_SAT}}$$

is now:

$$ V_{DC} < \frac{β_F V_{IN} R_{B2} R_C}{R_{B1}(R_{B2} + R_C)} \; + \; V_{CE\_SAT}$$


$$ I_M > 0.4A$$

To solve for \$R_{B1}\$ and \$R_{B1}\$:

$$ 0.4A ≥ I_M$$

until you isolate the \$R_{B1}\$ and \$R_{B1}\$ into a multi-variate:


$$\require{cancel} \xcancel{\frac{R_{B1}}{R_{B2}} \quad or \quad \frac{R_{B2}}{R_{B1}}}$$

is now

$$R_{B1} R_{B2}$$

You can do algebra enough, right?

I thought I already showed these things about BJT saturation being the minimum current that can be drawn:

with degeneration resistor:

$$ I_C = min(\frac{β_F(V_{IN} - V_{BE\_SAT})}{(β_F + 1)R_E}, \frac{V_{DC} - V_{CE\_SAT} - V_{IN} + V_{BE\_SAT}}{R_C})$$ ^ This one I showed already

without degeneration resistor (but with base resistor):

$$ I_C = min(β_F \frac{V_{IN}}{R_B}, \frac{V_{DC} - V_{CE\_SAT}}{R_C})$$ ^ This one I haven't

We can have a third case where there is no degeneration resistor and no base resistor and the base and emitter current are only limited by parasitic resistance, but I won't do that.

For the very complete equation you put together the \$I_M\$ above and the 2 separate cases for maximum currents (through the min() function).

For more accuracy, one can substitute \$V_{BE\_SAT}\$ and \$V_{CE\_SAT}\$ with the equations in Ebers-Moll model, with little or no modifications to the given equations above, but I haven't tried it myself.

ALSO, don't buy from Lees's Electronics, they might mistake to give you parts set aside for me and you might end up with faulty components.


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