Assuming e.g that one part of design transmits 8 bit data word at a time but receiver needs a 16 bit word, we would need to concatenate two 8 bit words together to create a 16 bit word. If both blocks work at same frequency, the receiver shall receive input word every other cycle.

In opposite case e.g where transmitter sends 16 bit word every cycle, the 8 bit receiver shall have to work at twice the frequency to be able to keep up with it. Or maybe data does not come every cycle.

Is there a term used to describe this conversion between data widths?

The first case is simpler, just concatenation. The second is more tricky to implement There maybe need to use some FIFO between the two as well.

  • \$\begingroup\$ The second one just requires the 16 bit design to work half as fast. So change the clock input to the 16 bit design, put one of these between the clock source and the clock input of the 16 bit design. Using counters with several bits (that D-flip-flop is a 1 bit counter) is a great way to synchronize several designs. - Regarding what the opposite of concatenation is called.. not sure. Maybe bad design? \$\endgroup\$ – Harry Svensson Nov 19 '17 at 2:43
  • \$\begingroup\$ Thanks, yes there are different ways to do this. I was wondering about what terminology is used to describe this data width change. Assuming we cannot change frequency of the two blocks. \$\endgroup\$ – quantum231 Nov 19 '17 at 2:46
  • \$\begingroup\$ Ah wait, there is a word for that! It's at the tip of my tongue. I think it starts with the letter F. Hmm, now when I think about, in this case maybe decimation would be a better fit. Ish. \$\endgroup\$ – Harry Svensson Nov 19 '17 at 2:50
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    \$\begingroup\$ This sounds similar to clock stretching that you see in I2C devices, but I'm not sure that is what you are after. There really isn't a conversion that goes on here, just manipulation of the clock on one end or the other since you only have a single data bus line (only 1 bit at a time, regardless of frequency). If you were changing a 16-bit parallel bus to an 8-bit one this might be considered multiplexing/demultiplexing possibly... \$\endgroup\$ – Ron Beyer Nov 19 '17 at 4:08
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    \$\begingroup\$ I would call this a specific form of (time) multiplexing / demultiplexing, or maybe (partial) serialization. \$\endgroup\$ – Wouter van Ooijen Nov 19 '17 at 10:44

Truncation was the word that was at the tip of my tongue. It's "limiting the number of digits right of the decimal point". So if we imagine that these 16 bits are in fixed point arithmetic and if all bits are = 1 then we got something close to 0.9999, then you could truncate the bits from 16 to 8. Aka throwing away 8 bits. Zeros and ones are just digits in base 2..

It's a cheaty way but not necessarily wrong. Not really right either.

The more correct term would in this case be decimation, the act of throwing away every X data of a signal, where X = "second" or "third" or etc. Since it's on an FPGA and you're streaming data it can be visualized as a signal.


Ah here's another definition of truncation called data truncation, the first one I linked was regarding math. This data truncation sounds like a perfect fit of what you are describing.

Or if you just want an umbrella name, there's data loss.

I believe all 4 would be acceptable in this case.

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