I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the received data.

For the project I am using the MachXO2 family of Lattice. In principle, I had thought of using an external 125 MHz oscillator to then pass it through the internal PLL and convert it to 250 MHz using the CLKOS output. My doubt is that in the datasheet it specifies that the DDR interface requires the use of a dedicated PCLK pin. I have made simulations of the code, and after trying to implement it, in the synthesis phase I get an error if I try to connect the CLKOS output of the PLL to the DDR receiver.

My question is, how can I approach this problem? Can I somehow use CLKOS from the PLL or is it impossible? Should I look for an external oscillator of 250 MHz and connect it to a PCLK pin?


1 Answer 1


Assuming your receiver is the MachXO2, you will use the transmitter 125 MHz clock to clock the IDDR registers. Then use a FIFO to cross data from the 125 MHz domain to the system clock domain. I suggest drawing a picture of the interfaces so people can help more.


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