3
\$\begingroup\$

I created the following circuit in Pspice: enter image description here

In the simulation profile I made sure that all flip-flops are initialized to 0. When I run this simulation I get the following error message: enter image description here

I just can't figure out what is the problem... can you help me with that? thanks a lot...

\$\endgroup\$
2
\$\begingroup\$

My opinion is as follows:

Your circuit works as an asynchronous binary counter, changing its count at every falling edge of the input clock (stimulus DSTM1), starting at 0,0,0 state (Q3,Q2,Q1 according to my schematic_diagram).

enter image description here

As soon as the count reaches 1,1,1, i.e. after ~3.5us, it comes to a "problem" because the inverted output Q3bar=L (signal clr) would immediately clear all the three flip-flops, and therefore, it tries to set back to Q3bar=H also itself.

enter image description here

The time of the generated impulse is too short to clear the flip-flops. The waveform diagram shows that the value of Q3 and 'clr' (Q3bar) is due to it undefined from that time on. That's why at the next counting edge at 4.5us the value of Q1 cannot be determined (see the waveform diagram - the red waveform Q1) - because of the 'PERSISTENT ERROR at "CLEAR" input of X_U1A' (your error message). When you prolong the clearing signal duration, it will clear the flip-flops properly and the problem disappears - see the modified schematic diagram, where the clr signal is hold at L level for one half of the clock period.

enter image description here

enter image description here

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.