1) I don't see why not. The article has the manufacturer's name on it, much more reputable than 'some guy off the internet'. Without actually building or simulating it, or doing calculations around R2/3 C2 values (the only bit that isn't 'obviously OK'), this guy off the internet (me) thinks it all looks perfectly plausible, the concept and block diagram are sound.
The fact they give distortion figures versus frequency strongly suggests it has been simulated and built, and works. Errors have been known to occur in data sheets, but with this simple circuit, and performance results, it would be taking caution too far to assume something was wrong at this stage.
2) No. The input to the whole circuit is a signal at the desired output frequency. The output signal syncs to the input signal.
3) 'The squarewave' doesn't exist externally, it's generated by the digital PLL comprising the 4046 and 4060.
The switched capacitor filter IC needs the 64x squarewave as its clock input. It strips all harmonics off the 1x squarewave at its signal input.
Having said the circuit looks sound, it is quite easy to mess things up when you build it. Building on breadboard, it's easy to mis-wire, and to blow up those CMOS ICs with static. When you lay out on a board, make sure the 64x clock is nowhere near the analogue output, otherwise you'll get pickup. The easiest way to get a clean ground is to use a ground plane. Keep the plane sacrosanct, don't shred it into a lace curtain by passing 'only one, OK then, just one more' track through it.
The 297 data sheet claims it will work down to 0.1Hz corner. As the full design only claims a minimum 20Hz frequency, this is all you should expect. The limitation is probably the PLL filter R2/3 C2, you would need to at least increase the value of C2 for lower frequencies, however then the circuit would respond more slowly.