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I am working on my first project in analog/board design, and although I know a decent amount of theory in electronics, I am lacking in practical experience.

I need an exact sine wave generator, and someone suggested looking at this:

https://www.maximintegrated.com/en/app-notes/index.mvp/id/4504

  1. First of all, can I trust this design to operate as is?

    This seems to be what I am looking for in terms of the output frequency range, but I have some questions about its operation

  2. From its description, I think that the input is a square wave and the output is a sine wave that is 1/64 of the frequency of the square wave. Is that correct?

  3. What is the point of the PLL+VCO (the first IC) of the design? Why not feed the square wave directly into the frequency divider?

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  • \$\begingroup\$ Looks like an app note created from an EDN article. I'd use either as a significant indicator it will work. \$\endgroup\$ – StainlessSteelRat Nov 21 '17 at 14:17
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1) I don't see why not. The article has the manufacturer's name on it, much more reputable than 'some guy off the internet'. Without actually building or simulating it, or doing calculations around R2/3 C2 values (the only bit that isn't 'obviously OK'), this guy off the internet (me) thinks it all looks perfectly plausible, the concept and block diagram are sound.

The fact they give distortion figures versus frequency strongly suggests it has been simulated and built, and works. Errors have been known to occur in data sheets, but with this simple circuit, and performance results, it would be taking caution too far to assume something was wrong at this stage.

2) No. The input to the whole circuit is a signal at the desired output frequency. The output signal syncs to the input signal.

3) 'The squarewave' doesn't exist externally, it's generated by the digital PLL comprising the 4046 and 4060.

The switched capacitor filter IC needs the 64x squarewave as its clock input. It strips all harmonics off the 1x squarewave at its signal input.

Having said the circuit looks sound, it is quite easy to mess things up when you build it. Building on breadboard, it's easy to mis-wire, and to blow up those CMOS ICs with static. When you lay out on a board, make sure the 64x clock is nowhere near the analogue output, otherwise you'll get pickup. The easiest way to get a clean ground is to use a ground plane. Keep the plane sacrosanct, don't shred it into a lace curtain by passing 'only one, OK then, just one more' track through it.

The 297 data sheet claims it will work down to 0.1Hz corner. As the full design only claims a minimum 20Hz frequency, this is all you should expect. The limitation is probably the PLL filter R2/3 C2, you would need to at least increase the value of C2 for lower frequencies, however then the circuit would respond more slowly.

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  • \$\begingroup\$ Maybe I understand less then I thought about this design. Can you please give me a more detailed explanation of what this circuit does/how it works? What exactly is the input 'SIG IN'? How exactly is the square wave created between the 4046 and the 4060? I understand that the third IC is an LPF designed to strip the square wave of its odd harmonics... \$\endgroup\$ – David Nov 21 '17 at 8:20
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    \$\begingroup\$ the 4046 works to force SIGIN and COMPIN to be at the same frequency. As VCOOUT is divided by 64 in the 4060, this forces VCOOUT to be 64x SIGIN. SIGIN is any signal that has the frequency you desire for the output, and sufficient amplitude to be recognised on the 4046 SIGIN input. Look at app notes for the 4046 for more details. If instead you already have a high frequency squarewave, say from a synth you want to divide down, then you can omit the 4046, and just use the 4060 and the 297. The 4046 is to allow a 1x input, rather than needing a 64x input. \$\endgroup\$ – Neil_UK Nov 21 '17 at 8:26
  • \$\begingroup\$ Thanks for you explanation of the circuit. So are you saying that SIGIN can be a square wave with 50% duty cycle or 10% or 90%, or a saw tooth wave, as long as the frequency is the one I want? Because it says in the the explanation "The fact that the filter's input signal is a square wave (with 50% duty cycle) helps this application, because a square wave contains only odd harmonics of the fundamental, and the lowest-frequency harmonic is the third, which is well within the filter's deep-attenuation range." \$\endgroup\$ – David Nov 21 '17 at 8:37
  • \$\begingroup\$ The 297 input is a squarewave with 50% duty cycle, because it's the output of the 4060 binary divider. I misunderstood that bit, and thought the 2nd harmonic wasn't in the stopband, but when I did the sums I notice even the 2nd harmonic falls within the proper -80dB stopband, so the 'no even harmonics' bit is true, but irrelevant, now fixed in my answer. The input to the 4046, SIGIN, can be anything the 4046 will lock to. It can be logic level or AC coupled low level, but the 4046 data sheet doesn't say how low level, or how extreme the duty cycle can be, not good, you'd have to experiment! \$\endgroup\$ – Neil_UK Nov 21 '17 at 10:22

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