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When you look at the newest consumer AMD and Intel chips with billions of transistors, what the (Pareto) breakdown of building blocks used? Or asking in another way, if you zoomed into a modern CPU what would be the building-block type breakdown per unit area (from occupying most area to least)?

Of course Cache would be the Nr 1 but what about the next 9 or so?

Is there a document which lists those out (per transistor count or per unit area from most to least)?

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Intel CPUs have the cost directly dependent to size of cache. The amount of die devoted to L1-L2-L3 cache can be as large as 50% or more. So the elementary block for the cache is multiport single bit SRAM cell with write-through/read through path. It can comprise may be dozens of transistors per bit of memory. And how it looks in schematics is possibly a trade secret.

Effectively everyone who buys contemporary CPUs pays mostly for this cache structures, as they consume most of die real estate. Intel and other CPU manufacturers are mostly in business of selling very large raw caches sprinkled with few CPU/FPU cores here and there. There are even DRAM bga solutions which can be soldered as stackable tier on top of CPU chips. One more evolutionary step and all large cpus will start directly compete with DRAM industry.

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  • \$\begingroup\$ Thanks for the detailed answer (also thanks to the comments above). I am curious about the distribution of transistors per building block in the actual cores (prediction logic, pipelines etc.) on a i7-3770, say. Maybe the Pentium layout quoted above is still representative today. Regarding your last comment: How will Intel be able to accommodate Gigabytes of DRAM on the die without making it huge? \$\endgroup\$ – Wuschelbeutel Kartoffelhuhn Jun 18 '12 at 22:50
  • \$\begingroup\$ They will stack the DRAM with chip-on-chip technology, this is my prediction. \$\endgroup\$ – user924 Jun 18 '12 at 22:52
  • \$\begingroup\$ @user924 My 2015 survey paper on DRAM cache confirms this prediction. Also, Intel's Knights Landing processor is said to use 16GB stacked DRAM cache. Also note: DRAM which was used only for 'main memory', is now being used for die-stacked 'cache' also, due to its high density. \$\endgroup\$ – user984260 Sep 24 '15 at 15:37

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