I'm transforming the design of a feedback controller(PI controller) which was already in Simulink, to FPGA using Xilinx System Generator. The main design problem i'm facing is the negative slack time. I'm adding delay blocks in the logical path in such a way that the inputs to a particular block(say AND gate) has the same delay. Is this the reason for getting negative slack?enter image description here. Since the logic is quite complex, i had to add many delays in different path to make it reach at the same time. In the attached figure shows an example of how the basic design is. The delay encircled in yellow is the additional delay added to make the output stable.

  • \$\begingroup\$ For what clock frequency you constrained the design to ? \$\endgroup\$
    – Mitu Raj
    Nov 23, 2017 at 17:27
  • \$\begingroup\$ 80 Megahertz (12.5 s) \$\endgroup\$ Nov 23, 2017 at 17:30
  • \$\begingroup\$ Why you added delay block ? Just by adding a delay block, you cant make sure that inputs will reach the AddSub block at the same time. Routing delays inside FPGA will vary. \$\endgroup\$
    – Mitu Raj
    Nov 23, 2017 at 17:42
  • 5
    \$\begingroup\$ …why are you applying a delay to a constant?? \$\endgroup\$
    – user39382
    Nov 23, 2017 at 19:22

1 Answer 1


It doesn't look like the delay you added after the Constant block will have any effect (there's nothing to delay - it's (apparently) just a constant signal). Is there more work happening in there that's not obvious?

The bigger question is what's the propagation time through those AddSub blocks? If the total delay from {In1,In2} to {Out1} through those two blocks is longer than a clock cycle, then a transition on those inputs isn't guaranteed to be reflected at the output within one clock. That's the negative slack, basically.

There can be designs that are intended to take multiple clock cycles (imagine your AddSub latched the inputs, processed them over a few cycles, then latched the results), but the constraints would need to be specified properly for that (it's not clear that's what's happening here).

Xilinx's Timing Closure User Guide can be helpful in debugging such issues.


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