I'm faced with a problem where we have an SPI NOR flash attached to an Intel I210 PCIe-ethernet adapter on a custom Cortex A9 based board. The SPI flash is normally used by the ethernet adapter to hold configuration data and firmware binary, but at the moment it's empty, in which case the ARM tools that Intel provided cannot touch the external SPI flash, and our ethernet chip now sits there unable to do anything helpful.
After digging around in the Intel chip's datasheet, I realised that there is a register with address offset 0x1201C called "FLA", and some bits in this register correspond with the sclk, miso, mosi and slave-select pins of the SPI flash. The datasheet recommends that, with an empty flash chip, the host should bit-bang commands to the SPI flash to enable writing to it through some other channels. I thought this would be a more promising approach than trying to port Intel's x86 drivers and tools to our board.
My problem is that, since the SPI flash operates at a much slower clock rate than the PCIe bus, how do I make sure that the slave-select and mosi signals arrive with sufficient setup and hold times relative to sclk?
Say, if I drive slave-select low in one memory-write operation and pulse the clock high in the next, does the PCIe infrastructure give any guarantee about the time between the packets arriving? Will it guarantee that the packet containing slave-select will arrive before the one containing the rising edge of sclk at all? Is using nanosleep() to try and add a delay between them a reasonable approach, for example?
I feel as if I've misunderstood some things and am going about it in a wrong way. How is this sort of bit-banging access usually done to ensure that the timing constraints are met?