first I have to say that I'm still a beginner and learning VHDL so any advice is a lot of help.
What I'm trying to do is control an image in a VGA monitor with an FPGA (Cyclone II), using a .mif file with the bits corresponding to that image and loading them into a ROM, so then I can read the values and show them.
My problem arises when I have to set the ports for the component that I'm using in my code..
architecture aa of VGA is --some signal declarations here component RomImage is port( address : in std_logic_vector(13 downto 0); inclock : in std_logic; outclock : in std_logic; qrom : out std_logic_vector(23 downto 0) ); end component; begin RomIm : lpm_rom generic map(lpm_file=>"GameOver.mif",lpm_numwords=>9500, lpm_width=>24, lpm_widthad=>14) port map(address=>address,inclock=>inclock,outclock=>outclock,q=>qrom); -- other process and logic -- Output logic (only red, same for blue and green) redout(9 downto 7) <= qrom(23 downto 21) when x>=225 and x<=415 and y>=250 and y<=300 else rojo(5 downto 3);
I don't really know what clock I have to use for the inclock and outclock, one of them is to read address and the other for the output q.
In the design I enter with a 50 MHz clock and then for the VGA clock I divide the frequency to obtain 25 MHz which is the one I need to make the screen work.
I would imagine that the screen sweep has to be synchronized with the frequency at which you have to read the values from the ROM.
Sorry if it's too much code or confusing, I'll try to expand if needed