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If a master is operating at 4MHz and the slave is at 16MHz the data should still be sampled at the speed of the SCLK pin, the frequency difference shouldn't matter right?

I used a Mikroe Dev board and tried to communicate to a CAN peripheral using SPI.
The board module operated @ 16MHz using a external oscillator while my MCU only used its internal 4MHz clock no commands worked until an external oscillator was used at 16MHz.

Can a master and slave operate at two different frequencies not the SCLK pin frequencies but the actual clock cycles frequency?

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    \$\begingroup\$ The clock for SPI is generated by master. For both directions. So the question seem to make no sense. If you are asking if the two chips can have different "cpu" clock - of course they can. And it is not related to SPI or whatever interface between them. \$\endgroup\$
    – Eugene Sh.
    Commented Nov 24, 2017 at 19:01
  • \$\begingroup\$ It's quite likely that the theoretical question you are asking is not directly rated to the observed issue. In any case, the situation is not specified precisely enough for the question to have a specific factual answer as is required on SE sites. \$\endgroup\$ Commented Nov 24, 2017 at 19:33

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It comes down to the speed of the peripheral you are trying to interface to. In general the microprocessor or port is at a multiple of the CAN frequency.

You have no problem communicating between SPI master to MCP2251. But 4MHz master would mean 500kHz (divide by 8) CAN-BUS peripheral. Odds are CAN peripheral did not recognize communications if it was 1MHz (or 250kHz).

Your microprocesor was attempting to communicate with a peripheral at a slower rate than the peripheral expected.

Mikro Dev CAN-SPI

Odds are the peripheral can be reconfigured to communicate at the lower speed if you need.

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You have three different frequencies here. The master has a clock frequency of 4MHz. The slave has a clock frequency of 16MHz. The SPI interface has a transfer clock determined by the SCLK line. This is generated by the master, and can be any frequency you choose as long as a) the master can make it and use it b) the slave can accept it and c) it's fast enough for your transfer speed requirements.

Usually SPI masters and peripherals have dedicated hardware shift registers, that handle the high speed requirements of the clock, and only demand or present whole bytes to the controller.

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  • \$\begingroup\$ It's common, especially in MCU implementations, for as SPI slave interface to actually be clocked by the internal clock, and merely sample the SPI clock. Or else to be clocked by a version of the SPI clock which has first been sampled by the internal clock. However, this doesn't seem to fit directly with the asker's situation - this rather looks like an XY problem. \$\endgroup\$ Commented Nov 24, 2017 at 19:32

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