Design a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9... Counter

Question

Design a counter: 12-10-8-6-4-2-0-1-3-5-7-9-11 using D Flip Flop.

My first approach is designing a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9 - 8 - 6 ... counter and display them on 7segment LED.

After writing down the binary code of these numbers above, I realize that they seem obeying a rule

1 0 0 0 (8)
0 1 1 0 (6)
0 1 0 0 (4)
0 0 1 0 (2)
0 0 0 0 (0)
0 0 0 1 (1)
0 0 1 1 (3)
0 1 0 1 (5)
0 1 1 1 (7)
1 0 0 1 (9)

It can be seeen that the LSB of the even numbers are always 0, while they're always 1 for the odd numbers. As for 3 left bits, they are symmetrical. So my idea for this problem is after counting from 8 downto 0, the LSB would change from 0 to 1, and start counting up (using 3 or 4 D-Flip-Flop and logic gates). But after writing down Next State Table, I face with the way to force my starting number to be 8.

Present State ---- Next State
0 0 0 0 ------------ 1 0 0 0 (next state is 8 if starting number is 0)
1 0 0 0 ------------ 0 1 1 0 (display 8, next state is 6)
0 1 1 0 ------------ 0 1 0 0 (display 6, next state is 4)
0 1 0 0 ------------ 0 0 1 0 (display 4, next state is 2)
0 0 1 0 ------------ 0 0 0 0 (display 2, next state is 0)
0 0 0 0 ------------ 0 0 0 1 (display 0, change LSB into 1, and activate counting up)

The problem here is that the state 0 0 0 0 is used twice (once for forcing starting number to be 8 and once for change LSB into 1) and I think my counter would get confused. So I wonder there are any ways to implement this kinda counter?

Thanks in advance for any of your answers.

---

My circuit works, bases on @Trevor's circuit Thanks all for your amazing ideas.

Answer 1

It sounds like you are expected to solve this with a state-machine type circuit, however it can also be done using a classical counter circuit.

The key to this problem is recognizing that for half the count you are inverting the counter output bits. Further, your output bit 0 is actually the most significant bit of the counter, it is just presented as the LSB.

As such you do not need to down count and then up count. A classic synchronous D-Type counter with some XOR invertors will suffice for the counting sequence.

simulator.io

The additional gates on the output detect the carry condition that forces the inputs to D-Type back to the start number.

Note also, I have inverted the bottom flip-flop. Since it turns out your initial condition for your 12....11 sequence is actually 1 on the counter, not 0, this effectively gets you the start-up condition you desire, at least in the simulator. I also added a reset pulse line just for good measure.

Of course another column of D-Types latched on the other edge of the clock at the output would make it even better.

Answer 2

Given it is an assignment, I'm not going to work through the logic. However in all such questions you can boil it down to a circuit with two steps:

1. You have a binary 0 to n-1 counter, where n is the number of required states (13 in your case). This can be a bog standard synchronous binary counter that starts at 0000 and then when it reaches n is reset back to 0000.

2. A combinational logic circuit that maps the values from the counter to the output values. The structure of this can be discrete logic gates, the circuit for which can be derived using Karnaugh Maps - one map per bit in the output. Alternatively it could be a simple ROM with the mapping stored in it, where the address lines go to the counter, and the data lines are your output.

This approach will be far simpler and far more generic (think flexible) than using hundreds of shift register bits.

Answer 3

The most boring solution, and the one that I'd actually recommend, to this is simply to build a 8 bit wide, 13 stages deep, circular shift register, where seven bits each represent the on/off state of one of your 1er seven LED segments, and one segments represents the two segments you need to switch on to display a 1 in the 10ers.

In effect, that would just be eight 13-stage shift registers in parallel. Shift registers are trivial to implement using D FFs, so, here you go:

^{simulate this circuit – Schematic created using CircuitLab}

The problem would be to get the initial values into that shift register, but you could just declare register have the right reset values, and be done with it. Nothing says you can't.

Of course, 8·13 = 104 shift registers might not be beautiful, but nothing in the assignment says beautiful is better than flexible, fast, or easy.

• Flexible: With this circuit, you can implement any 13-step sequence on a shift register.
• Easy: Since you directly work with the on/off state of the 7 segment displays, you avoid the overhead of having to convert anything from one representation of a number, to another.
• Fast: The clock speed of this is limited only by the timing of a single flip flop, and that means this implementation is provably the fastest of all implementations that involve at least one D-flip flop. Not that clock speed matters for the problem at hand, but again, you get the gist, your problem statement doesn't define the design goals.

Since this is a purely academic problem, feel free to optimize the hell out of this.

Answer 4

You may look for simplifications.

For example, you may find that part of the counter simply counts up and down in a straightforward sequence; there are patterns (even TTL logic chips) which you can use as straight up-down counters.

For that part of the counter, you simply need to detect the two end conditions and set a bit which controls the up/down count function.

For the remaining bit, can you identify a pattern or regularity in its output? Is it easily derived from the up/down counter and/or its control logic?

This is often more work than a simple counter driving a lookup table, but it probably yields a smaller solution.

Answer 5

To extend on Tom's excellent answer:

If the problem is to build a circuit with the least possible logic elements, you might want to avoid that 0…12 counter (which will need to be a four bit counter), but instead use a linear feed back shift register to generate the different states, and deal with the fact that they aren't sequential in the combinatorial logic.

This was a common trick that you did when you were doing thing like taking sound samples from a ROM to generate a periodic signal back in a time where the wafer real estate of a few halfadders would hurt you economically. You'll quite possibly still find that trick in modern ICs that need to do similar task (ie. generation of a periodic output sequence) at a very high speed, or on a very tight energy budget.

I honestly don't think your school expects you to design something like that at this point, but I think it's really worth knowing that you can, with a shift register of \$N\$ stages, find a Linear Feedback Shift Register configuration that yields a cycle of \$2^N -1\$ different states. This really has very many applications (especially in digital communication), and you're pretty likely to encounter these later on in your studies.

---

Answer 6

USING D FLIP FLOP.. Designing this counter is very easy.. You need to understand some basic concepts of state machines before solving it(NOTE-you can use truth table for logic simplification, and sorry for not drawing the logic) here is the solution

And here is the basic block diagram of the state machine/Arbitrary sequence counter