I just started to learn the sequential logic and I am a little bit confused of the difference between the latch and flipflop. More specifically, I am confused about the difference between edge triggered and level triggered.
So, I learned master slave flip flop first other than other flip flop. Then, I understood pretty well why master slave flip flop is edge triggered. I think it is the NOT gate of the clock signal to the second component that makes it edge triggered.(Not sure whether that second or first component is D flip-flop or D latch either)
However, then I came to learn about this SR flip-flop and even D flip-flop. And suddenly, I got confused about the difference between edge triggered and level triggered.
How is this SR flipflop edge triggered? Shouldn't it be level triggered since as long as the clock signal is HIGH, everytime the input changes, the output will respond to it.
I think flip-flop is always edge-triggered? Am I misunderstanding something?