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I'm interested in calculating series termination resistors for my communication lines for a system I'm designing based on the Zynq-7000 SoC. The system runs on a 33 MHz clock but I'm sure the bandwidths I need to consider are much greater due to the rise time of the signals (I'm interested in just the processor right now). I tried looking for rise times of this SoC's signals, and even tried to find it for generic ARM cortex A9 processors, but wasn't able to come up with anything.

How would I go about finding the rise time to ensure the termination resistance I implement are appropriate for my system?

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The Zynq-7000 is FPGA. All I/O on Xilinx FPGAs are configurable to meet two dozen interface standards. Every I/O configuration would have its own drive strength (impedance) and timing. There is additional document on Xilinx website on how to configure GPIOs on this particular family, and what their parameters could be.

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  • \$\begingroup\$ NOTE: Edge rate has no relevance to selection of termination resistors. Characteristic impedance of PCB traces has. \$\endgroup\$ – Ale..chenski Nov 27 '17 at 7:38
  • \$\begingroup\$ Really? I was reading around and found this post from which I learned about rise time effects on transmission lines. Also, the signals I'm concerned about are coming out of the MIO pins of the A9 processor of the Zynq, not the FPGA. \$\endgroup\$ – akivjh Nov 27 '17 at 15:23
  • \$\begingroup\$ @akivjh, all this dancing around overshoots are for unterminated transmission lines with out-of-whack characteristic impedance. If you are targeting DDR3 etc, you must control your traces in accord with recommendations, consult with UG586, xilinx.com/support/documentation/ip_documentation/…. Xilinx will provide proper port impedances, and memory modules will do the same. Your job is to make right PCB traces. Other direct interfaces from A9 core also should meet corresponding timing standards. \$\endgroup\$ – Ale..chenski Nov 28 '17 at 1:55
  • \$\begingroup\$ yes our impedances are tightly controlled for LPDDR2 design for the zynq. Thanks for the link but again it relates only to the FPGA, while the functionality I'm concerned about is to do with the processor, am I missing something here? \$\endgroup\$ – akivjh Nov 30 '17 at 1:41
  • \$\begingroup\$ @akivjh, isn't the DDRx interface coming from the processor? What is your concern then? \$\endgroup\$ – Ale..chenski Nov 30 '17 at 2:52

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