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I have been researching via stitching for the GND planes around the edges of the PCB for the past while. I have found alot of resources on the topic, such as the making the spacing distance equal to the smallest dominant wavelength divided by 20. However, I have also seen it said numerous times that if you place the vias too close together you can actually make the emissions worse than if you had no vias. I am wondering how this is possible, and if anyone has any half decent explanation for how too many vias can make the EMI worse.

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    \$\begingroup\$ Citation for making it worse? \$\endgroup\$ Nov 28, 2017 at 21:33
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    \$\begingroup\$ In the context of your question, I don't see how the vias would make it worse. But in OTHER contexts, vias definitely can create problems. When multiple non-ground vias are placed so close together that their ground layer keepouts merge together to make a slot, the ground layer impedance for some return currents can be greatly increased. That is why we need a citation. \$\endgroup\$
    – user57037
    Nov 28, 2017 at 22:12
  • \$\begingroup\$ The concept of vias which are inductive is the reduce the inductance of the ground plane by reducing the loop area and also parallel vias which reduce ESL. But if you consider the edge of two ground planes as a slot antenna, I suppose too many vias near the edge might affect edge emissions from edge via radiations but I have not seen this. \$\endgroup\$ Nov 28, 2017 at 23:51
  • \$\begingroup\$ A lot of this stuff is anecdotal.. or even voo-doo \$\endgroup\$
    – Trevor_G
    Nov 28, 2017 at 23:58
  • \$\begingroup\$ I haven't heard such things, "when 2 GND planes are stiched by GND vias , if pitch of the vias are decreased or number of vias connecting increased -> emi worsens" \$\endgroup\$
    – user19579
    Nov 22, 2018 at 5:41

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The parastics for vias look like the circuit below. With the vias the same size and making the grid smaller would only reduce the inductance and resistance between vias.

schematic

The via sizing will make a difference, making the via smaller (with the height the same increases the inductance. However, there are more vias so over all the inductance drops. The specific frequency does matter, and can be estimated per your application. Since the values are in the uΩ, pF and pH range, the time to care about this is when you are dealing with microwaves.

enter image description here Source: https://www.microwaves101.com/encyclopedias/microstrip-via-hole-inductance

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As it is made clear in the answers and comments, more vias reduce the overall impedance between the planes at the edge of the PCB. So the specific scenario where you read that should be further documented.

The only scenario where I can see such problem happening is if you are “lucky” enough to place them spaced in a specific resonance that coincides with a significant harmonic of your board emission profile.

Contrary to popular belief, symmetry is a problem, not an advantage. By placing elements equidistant from each other, you are actually creating a resonant structure, with nulls and peaks at specific frequencies. Generally too high a frequency to be a problem, unless Murphy intervenes.

To make sure to avoid this you have two choices, either place the vias in semi-random distances, that way any resonance will be shallower and placed at a minimum common multiple of the spacing (prime number spacing is a good one for that reason).

Or do what is commonly seen in high-frequency PCBs, use two separate rows of vias, each one with different spacing and via sizes. That way the resonances of one structure will be canceled by the nulls of the other.

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