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It's my first time coding in VHDL and I ran to some problem I have absolutely no idea how to solve. When I try to compile my code in modelsim it gives me "No Feasible Entries for Subprogram rising_edge". Here's my code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

ENTITY cnt IS
    PORT(
        clk, res_cnt, cnt_en : IN BIT;
        dataOut: OUT INTEGER
    );
END cnt;

ARCHITECTURE base OF cnt IS
    SIGNAL data: INTEGER;
BEGIN
    PROCESS (clk)
    BEGIN
        IF rising_edge(clk) THEN
            data <= 1 WHEN res_cnt = '1' ELSE (data + 1);
        END IF;
    END PROCESS;

    dataOut <= data;
END base;
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  • \$\begingroup\$ package numeric_bit instead of numeric_std. \$\endgroup\$ – user8352 Nov 29 '17 at 8:48
  • \$\begingroup\$ I'm not using numeric_bit nor numeric_std.. @user8352 \$\endgroup\$ – Bat Nov 29 '17 at 10:24
  • \$\begingroup\$ rising_edge is found in numeric_bit. You weren't using any of those in your context clause. \$\endgroup\$ – user8352 Nov 29 '17 at 13:43
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Don't use BIT type, use STD_LOGIC instead. That's probably why you have your error. There is no rising_edge routine for BIT in libraries you are using, but there surely is for std_logic.

Besides, why did you include IEEE.MATH_REAL, IEEE.std_logic_unsigned, and IEEE.std_logic_arith? You are not using it, and actually you should never include the latter two (this packages are not in IEEE standard). Use IEEE.numeric_std instead.

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  • 1
    \$\begingroup\$ As you sort of say, std_logic_1164 contains a function for rising_edge(std_logic) but not for rising_edge(bit) so that's the problem. Using std_logic_unsigned and std_logic_arith is a lengthy and very separate debate but OP is fine to use them. They've accompanied synths/sims for twenty years and are never going to be removed so they're no less standard. \$\endgroup\$ – TonyM Nov 29 '17 at 8:36
  • \$\begingroup\$ Well, I meant they are not really in IEEE standard, and should not be used in new design. I think it's good to tell it someone who might have been (like me in the past) mislead by old teachers at school, or some bad examples. But you are right in that it's fine to use it, if you just want your design work, and not go with good practices, that makes design less error prone. \$\endgroup\$ – Staszek Nov 29 '17 at 12:16
  • \$\begingroup\$ It's a much-debated thing but I've found the opposite to what you're saying, Staszek. But rather than start a discussion here and hijack a different question, please feel free to go to chat on this. Otherwise I'll leave it there but thanks for your time and opinion :-) \$\endgroup\$ – TonyM Nov 29 '17 at 15:05

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