# No Feasible Entries for Subprogram “rising_edge”

It's my first time coding in VHDL and I ran to some problem I have absolutely no idea how to solve. When I try to compile my code in modelsim it gives me "No Feasible Entries for Subprogram rising_edge". Here's my code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

ENTITY cnt IS
PORT(
clk, res_cnt, cnt_en : IN BIT;
dataOut: OUT INTEGER
);
END cnt;

ARCHITECTURE base OF cnt IS
SIGNAL data: INTEGER;
BEGIN
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
data <= 1 WHEN res_cnt = '1' ELSE (data + 1);
END IF;
END PROCESS;

dataOut <= data;
END base;

• package numeric_bit instead of numeric_std. – user8352 Nov 29 '17 at 8:48
• I'm not using numeric_bit nor numeric_std.. @user8352 – Bat Nov 29 '17 at 10:24
• rising_edge is found in numeric_bit. You weren't using any of those in your context clause. – user8352 Nov 29 '17 at 13:43

Don't use BIT type, use STD_LOGIC instead. That's probably why you have your error. There is no rising_edge routine for BIT in libraries you are using, but there surely is for std_logic.
Besides, why did you include IEEE.MATH_REAL, IEEE.std_logic_unsigned, and IEEE.std_logic_arith? You are not using it, and actually you should never include the latter two (this packages are not in IEEE standard). Use IEEE.numeric_std instead.