# Simualtion stops at time 0 after a real to real multiplication!

In my project, which compiles fine on ModelSim, when I try to simulate my code it gives me:

Here is my code for multiplier:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;

ENTITY mult IS
PORT(
a, b: IN REAL;
dataOut: OUT REAL
);
END mult;

ARCHITECTURE base OF mult IS
BEGIN
dataOut <= a * b;
END base;


and this is my memory which derives a and b:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;

ENTITY memory IS
GENERIC(
memCapacity: INTEGER := 8
);
PORT(
w, r: IN BIT;
dataIn: IN REAL;
dataOut: OUT REAL
);
END memory;

ARCHITECTURE base OF memory IS
TYPE memBlock IS ARRAY (INTEGER RANGE <>) OF REAL;
SIGNAL mem: memBlock(memCapacity DOWNTO 0);
BEGIN
PROCESS (w, r)
BEGIN
IF (w = '1') THEN
ELSIF (r = '1') THEN
END IF;
END PROCESS;
END base;


Your simulation is probably working correctly though unless you post an [MCVE] we can't be completely be sure..

TYPE memBlock IS ARRAY (INTEGER RANGE <>) OF REAL;
SIGNAL mem: memBlock(memCapacity DOWNTO 0);


There are no initial values specified for the contents of mem, so each value in the array is initialised to the default, which is REAL'LEFT, or a rather large negative number.

Presumably your testbench initialises the values on ports a and b the same way. Multiplying them together will give an extremely large positive number, with the result shown.

You can initialise signals in the declaration, for example,

SIGNAL a_test, b_test : REAL := 0.0;
SIGNAL mem: memBlock(memCapacity DOWNTO 0) := (others => 0.0);


will clear the array's contents, as well as the a_test signal(etc) you connect up to ports a and b in your testbench.

It was kinda weird. At last, I drived 1.0 on my memories output all the time; so now, the unit is completely out of circuit and it is only a wire connected to 1.0. But it couldn't solve it either. Then I declared default values for all my signals but it still wasn't helpful. Then I changed my code of multiplier to this code:

BEGIN
PROCESS
BEGIN
wait for 0 ns;
dataOut <= a * b;
wait on a, b;
END PROCESS;
END base;


It works while logically it's the same as the previous code.

• A default value to a port of mode in is used when there is no other driving value. See IEEE Std 1076-2008 14.7.3.2 Driving values para 3 e). "If S is a basic signal: — If S has no source, then the driving value of S is given by the default value associated with S (see 6.4.2.3)." It's the actual that wants to have the an initial value. Note Brian's answer writes of the testbench declarations where the actuals of a and b would be found. The same holds true for addition. – user8352 Feb 1 '18 at 15:49