# How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that my receiver circuit does not support this and expects the clock to always be running so I wish to build some sort of buffer circuit that "continues" the clock in those periods where it is turned off.

Here is what the input signal looks like:

In the time when the input clock is on, I wish to have low propagation delay (ideally passing the input clock right through). However, when the input clock is off, I want the output clock to continue at the "last seen frequency"--skew does not matter much. Once the input clock comes back up, I want it to match the phase again. From the D-PHY standards, I think I have 85ns + 6 clock periods to do this.

A potential solution I thought of is to use a 2:n clock buffer with a select pin along with a PLL. The output of the buffer will be the PLL (and my application) and the inputs of the buffer will be the source clock and the PLL output. Then I can set the select pin to my DCLK+ so it will automatically select the PLL when it goes high. Will this work or is there some obvious problems?

• I read this ti.com/lit/an/snaa208/snaa208.pdf and it seems like clock jitter cleanup with two clocks and automatic switching seems to do what I want. Second clock will just be the output. However this solution seems pretty expensive--the cheapest IC that does this seems to be >$6 a piece. – Yifan Dec 1 '17 at 4:03 • Wow, that sounds great if it'll do what you need. As a one off,$6 is a great deal. If you're actually trying to sell a device in large volume from this, then you'd be stuck building your own solution. Definitely weigh engineering costs into your price comparisons though. – horta Dec 1 '17 at 5:04
• Yeah it's actually more like $10 if you only buy one lol. Yeah it's a one-off thing, but the price just makes me wonder if it's an overkill for what I need. – Yifan Dec 1 '17 at 5:16 • If it will do everything you need it to, understand that$10 is extremely cheap. You're asking for an intelligent PLL circuit. Creating that in discretes alone would likely cost much more than that, take up much more space on a pcb, and probably take a lot of engineering hours. Another solution might be to use a fast uController to spoof the clock if its clock is faster than the clock you're spoofing. Even here, although much cheaper and simpler, you're still looking at a decent amount of engineering effort (more from the software side). – horta Dec 1 '17 at 14:53
• I've been reading more on the subject and it seems like I can use a normal PLL with a very low loop bandwidth which will respond slowly to the sudden frequency change (300MHz => 0Hz) and "ignore" it. – Yifan Dec 2 '17 at 0:25