can this layout do what I need? I know there is problem with the last stage, the last opamp should give me gain: k2, to get V1 * V2 but I don't know that the value of k2?
The K values control the R value which controls the diode current which can lead to errors if there is self heating which is the NTC Shockley Effect.
But if diode current is too low then the OP Amp input offsets become significant compared the the log1, log2 outputs.
The diode dynamic resistance also drops with rising log(current) until saturated where the bulk resistance limits the minimum resistance. From this I know ESR is ~ 1/Pd (rated) so depending on your specs for input range and error budget, you need to operate well below max rated Pd such as < 1% Pd.
The bulk size and Pd rating of the diode affects the thermal resistance and bulk resistance or ESR, and also junction capacitance and bandwidth. So this is another tradeoff for diode size vs bandwidth vs temp rise.
One usually starts with a spec for Input and Output voltage range and max error vs input. Then determines the required input bias current and offset must be to achieve this.
Then finally choose a max temp difference of the log and antilog diodes to avoid gain and offset errors. Matched temperature by thermal coupling is desired or minimize self heating for low T rise. This then limits the didoe current and determines the Vin/R values for your design.
As a rule of thumb, Vf will probably be around <= 0.65V for silicon and Pd will probably <1% of the diode rated power. But this depends on your thermal design.
So write some specs for this design In/Out and error budget then compute K2 from the above considerations for current limits. then choose Op Amps that satisfy the offset errors implied by your specs.
Then verify your design specs with sweeping voltages on the inputs and compute the gain and offset errors vs input.