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This question may sound very simple but the code I wrote for a seven segment display adder with pushbuttons in VHDL takes so long to generate a bitstream. I reset and tried again several times but it has been about 4 hours now and the bitstream is not generated. I don't think the code will be necessary for this question but if it matters in the answer of the question, I would love to include it. I am using Vivado 2017.2 wrote two source and a constraints file for the FPGA Basys3 and the language that I am using is VHDL.

Thanks in advance for any suggestion.

Main code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    port(b1,b2,b3,b4 : in STD_LOGIC;
          clk         : in STD_LOGIC;
          sseg        : out STD_LOGIC_VECTOR(0 to 6);
          anodes      : out STD_LOGIC_VECTOR(3 downto 0);
          reset           : in STD_LOGIC
          );
end main;

architecture Behavioral of main is
    signal bcd1, bcd2, bcd3, bcd4 : STD_LOGIC_VECTOR (3 downto 0);
    signal clk2 : STD_LOGIC;
    signal pushbuttons : STD_LOGIC_VECTOR(3 downto 0);
    signal db_pushbuttons : STD_LOGIC_VECTOR(3 downto 0);
    signal counter : STD_LOGIC_VECTOR(1 downto 0);
    signal clk_divider : STD_LOGIC_VECTOR(20 downto 0);
    component Debounce is
        port( cclk : in STD_LOGIC;
                inp : in STD_LOGIC_VECTOR(3 downto 0);
                cclr : in STD_LOGIC;
                db  : out STD_LOGIC_VECTOR(3 downto 0)
                );
    end component;
begin
    pushbuttons <= b4 & b3 & b2 & b1;
    Db : Debounce port map
            ( cclk => clk2,
              inp => pushbuttons,
              cclr => reset,
              db  => db_pushbuttons);

process (clk)
begin
    if rising_edge(clk) then
        if clk_divider <= "1100001101010000" then
            clk_divider <= clk_divider + 1;
            clk2 <= '0';
        else
            clk_divider <= (others => '0');
            clk2 <= '1';
        end if;
    end if;
end process;

process (clk2, reset)
begin
    if reset = '1' then
        -- do something here
        bcd1 <= "0000";
        bcd2 <= "0000";
        bcd3 <= "0000";
        bcd4 <= "0000";
    elsif rising_edge(clk2) then
        counter <= counter + 1;
        if db_pushbuttons(0) = '1' then -- db_b1
            if bcd1 <= "1000" then
                bcd1 <= bcd1 + 1;
            else
                bcd1 <= "0000";
            end if;
        elsif db_pushbuttons(1) = '1' then -- db_b2
            if bcd2 <= "1000" then
                bcd2 <= bcd2 + 1;
            else
                bcd2 <= "0000";
            end if;
        elsif db_pushbuttons(2) = '1' then -- db_b3
            if bcd3 <= "1000" then
                bcd3 <= bcd3 + 1;
            else
                bcd3 <= "0000";
            end if;
        elsif db_pushbuttons(3) = '1' then --db_b4
            if bcd4 <= "1000" then
                bcd4 <= bcd4 + 1;
            else
                bcd4 <= "0000";
            end if;
        end if;
    end if;
end process;

process (counter, bcd1, bcd2, bcd3, bcd4)
    variable display : STD_LOGIC_VECTOR(3 downto 0);
begin
    case counter is
        when "00" => anodes <= "1110"; display := bcd1;
        when "01" => anodes <= "1101"; display := bcd2;
        when "10" => anodes <= "1011"; display := bcd3;
        when "11" => anodes <= "0111"; display := bcd4;
        when others => null;
    end case;

    case display is
        when "0000" => sseg <= "0000001"; --0
        when "0001" => sseg <= "1001111"; --1
        when "0010" => sseg <= "0010010"; --2
        when "0011" => sseg <= "0000110"; --3
        when "0100" => sseg <= "1001100"; --4
        when "0101" => sseg <= "0100100"; --5
        when "0110" => sseg <= "0100000"; --6
        when "0111" => sseg <= "0001111"; --7
        when "1000" => sseg <= "0000000"; --8
        when "1001" => sseg <= "0000100"; --9
        when others => sseg <= "0010000"; --e, represents error
    end case;
end process;
end Behavioral;

Debounce code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Debounce is
    port(cclk       :   in STD_LOGIC;
          inp    :  in STD_LOGIC_VECTOR(3 downto 0);
          cclr  :  in STD_LOGIC;
          db     :  out STD_LOGIC_VECTOR(3 downto 0)
         );
end Debounce;

architecture Behavioral of Debounce is
    signal delay1, delay2, delay3 : STD_LOGIC_VECTOR(3 downto 0);
begin
    process (cclk, cclr)
    begin
        if cclr = '1' then
            delay1 <= "0000";
            delay2 <= "0000";
            delay3 <= "0000";
        elsif rising_edge(cclk) then
            delay1 <= inp;
            delay2 <= delay1;
            delay3 <= delay2;
        end if;
    end process;
    db <= delay1 and delay2 and delay3;
end Behavioral;

Constraints:

## Switches
set_property PACKAGE_PIN V17 [get_ports {reset}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {reset}]
set_property PACKAGE_PIN V16 [get_ports {cclr}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {cclr}]
##7 segment display
set_property PACKAGE_PIN W7 [get_ports {sseg[0]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sseg[0]}]
set_property PACKAGE_PIN W6 [get_ports {sseg[1]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sseg[1]}]
set_property PACKAGE_PIN U8 [get_ports {sseg[2]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sseg[2]}]
set_property PACKAGE_PIN V8 [get_ports {sseg[3]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sseg[3]}]
set_property PACKAGE_PIN U5 [get_ports {sseg[4]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sseg[4]}]
set_property PACKAGE_PIN V5 [get_ports {sseg[5]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sseg[5]}]
set_property PACKAGE_PIN U7 [get_ports {sseg[6]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sseg[6]}]

#set_property PACKAGE_PIN V7 [get_ports dp]                         
#   set_property IOSTANDARD LVCMOS33 [get_ports dp]

set_property PACKAGE_PIN U2 [get_ports {anodes[0]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {anodes[0]}]
set_property PACKAGE_PIN U4 [get_ports {anodes[1]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {anodes[1]}]
set_property PACKAGE_PIN V4 [get_ports {anodes[2]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {anodes[2]}]
set_property PACKAGE_PIN W4 [get_ports {anodes[3]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {anodes[3]}]


###Buttons
##set_property PACKAGE_PIN U18 [get_ports btnC]                     
#   #set_property IOSTANDARD LVCMOS33 [get_ports btnC]
set_property PACKAGE_PIN T18 [get_ports b1]                     
    set_property IOSTANDARD LVCMOS33 [get_ports b1]
set_property PACKAGE_PIN W19 [get_ports b2]                     
    set_property IOSTANDARD LVCMOS33 [get_ports b2]
set_property PACKAGE_PIN T17 [get_ports b3]                     
    set_property IOSTANDARD LVCMOS33 [get_ports b3]
set_property PACKAGE_PIN U17 [get_ports b4]                     
    set_property IOSTANDARD LVCMOS33 [get_ports b4]
\$\endgroup\$
  • \$\begingroup\$ 4 Hours is long for something trivial, but if the code or constraints result in a very full FPGA or one that has trouble meeting timing then build times (Particularly P&R) can get very long. Code and Constraints files please. Also, what computer are you using and how much RAM? \$\endgroup\$ – Dan Mills Dec 4 '17 at 14:55
  • \$\begingroup\$ @DanMills I am using Asus Intel core i5 with 8 gb ram and I included the code in to the question \$\endgroup\$ – Ekin Alparslan Dec 4 '17 at 15:09
  • \$\begingroup\$ Sounds like a simple error is not being reported. ( no code (; \$\endgroup\$ – Sunnyskyguy EE75 Dec 4 '17 at 15:12
  • \$\begingroup\$ Clock dividers in fabric like that are generally a really bad idea, much better to do a clock enable as it avoids clock in the fabric logic (that makes timing closure a pain), but I don't think that is your problem. Does it manage to get to the start of P&R without any errors or warnings that you do not understand (And what is the logic utilisation at that point)? I do not see an initialisation for clk_divider so it will likely start out as "UUUUUU...", not sure off the top of my head how that will synthesise with <= on a std_logic_vector (I would have used an unsigned here). \$\endgroup\$ – Dan Mills Dec 4 '17 at 16:06
  • \$\begingroup\$ Where do you constrain the clock frequency? In fact I don't see clk in the constraints file at all? \$\endgroup\$ – Dan Mills Dec 4 '17 at 16:15

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