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My teacher provided this as part of printed notes where he writes there is no tristate during the T2 state of Memory Write Cycle. I am quite confused about why it is so.

After a short search in the internet, I didn't find any such statements anywhere. Can the tristate exist in T2 too or is this optional? If it is true, why is it so?

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Obviously, there can be no "tristate" on AD[7:0] during either T2 or T3, because the CPU must use those lines to drive the data that is to be written to memory. The data needs to be valid for the duration of the WR- pulse and a little beyond.

What the footnote is saying is that while there's a transition between the low-order address values and the data values during T2, the bus is never actually "not driven".

A more detailed timing diagram would show a certain amount of hold time for the address bits following ALE. It would also show a certain amount of setup time for the data bits with respect to WR-. In between, the bus values are "undefined", but not high-impedance. In the diagram, this difference is denoted by the solid line before vs. the dotted line after the DATA bits on AD[7:0].


There's actually a subtle reason that they felt the need to add the footnote. Sometimes a system designer would rely on the fact that bus capacitance effectively extends the hold time when a bus driver switches off (tristates). In this case, they're explicitly stating that this is not true during this type of cycle.

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  • \$\begingroup\$ would you say the same for Memory read cycle too? is Tristate not allowed there too? What about IO Write Cycle? \$\endgroup\$ – bikalpa Dec 5 '17 at 7:05
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    \$\begingroup\$ Why aren't you getting this? Any bus can have only one driver enabled at any given time. In any cycle in which data is being transferred from the CPU (memory or I/O write), the AD[7:0] bus must be driven by the CPU during T2 and T3 -- no tristate. When data is being transferred to the CPU (memory or I/O read), the CPU must tristate the AD[7:0] bus during T2 and T3 so that an external device can put its data there and the CPU can capture it. \$\endgroup\$ – Dave Tweed Dec 5 '17 at 12:39
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I think that at the end of the T1 state the processor removes the lower-order address and immediately places the data on the bus.

I suspect the timing diagram is a little "off" and the words are an attempt to fix it without paying the graphic artist..

Compare this 8085 timing diagram:

enter image description here

Note that the lower order address persists past the rising edge of the clock, so there is lots of setup time and a bit of hold time available to latch the lower order address before the data appears.

Anyway, the line down the middle between high and low should be taken to indicate that the data is invalid, not that the bus is tristated, but it makes very little practical difference.

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