Obviously, there can be no "tristate" on AD[7:0] during either T2 or T3, because the CPU must use those lines to drive the data that is to be written to memory. The data needs to be valid for the duration of the WR- pulse and a little beyond.
What the footnote is saying is that while there's a transition between the low-order address values and the data values during T2, the bus is never actually "not driven".
A more detailed timing diagram would show a certain amount of hold time for the address bits following ALE. It would also show a certain amount of setup time for the data bits with respect to WR-. In between, the bus values are "undefined", but not high-impedance. In the diagram, this difference is denoted by the solid line before vs. the dotted line after the DATA bits on AD[7:0].
There's actually a subtle reason that they felt the need to add the footnote. Sometimes a system designer would rely on the fact that bus capacitance effectively extends the hold time when a bus driver switches off (tristates). In this case, they're explicitly stating that this is not true during this type of cycle.