I'm trying to learn Verilog and FPGA and just bought my first FPGA. It's a Lattice iCEstick.

It comes with a 12Mhz clock but I wonder If I can sample synchronous inputs with a clock faster than that. I don't know much about FPGAs but I think that the onboard clock is just a tool you can use but some parts of the design can use another external clock or no clock at all. I'm thinking about counting pixels in a HDMI connection, for example. It might use a higher frequency.

I guess heat and logic gate change and stabilization time might limit the clocks frequencies.

Am I right about these things? How can I know the limits?

Thank you

  • 1
    \$\begingroup\$ You can know the limits reading the datasheet of the device you are using. 12 MHz is fairly low, I expect a PLL to be present in your FPGA, and the maximum clock frequency can be up to a few 100 MHz, if you want a reliable design at least. \$\endgroup\$ Dec 5, 2017 at 13:04
  • \$\begingroup\$ Check if PLL is available as soft core in your fpga 's design suite \$\endgroup\$
    – Mitu Raj
    Dec 5, 2017 at 13:21
  • \$\begingroup\$ FPGA PLLs are usually NOT soft cores, there is generally actual specific hardware for these things. Usually you instantiate some sort of 'clock manager' block (The name varies depending on the vendor) that can take your 12MHz board clock and multiply it up to something more reasonable for internal use (50MHz-200MHz or so is typical). \$\endgroup\$
    – Dan Mills
    Dec 5, 2017 at 14:42
  • \$\begingroup\$ I had to search what is a soft core. :D Link here for the case someone else doesn't know it. electronics.stackexchange.com/questions/55377/… \$\endgroup\$
    – aalku
    Dec 5, 2017 at 16:55

1 Answer 1


A quick look at the datasheet for your part page 3-16 shows a maximum input clock of 133Mhz. There are two analog PLLs and the max frequency they can be run at is 275Mhz with the global clock buffer being the same 275Mhz max. CMOS inputs max out at 250Mhz, and LVDS at 400Mhz.

Now this does not mean your design will run at 275Mhz. Depending on the complexity you may only be able to close timing much lower than that or not at all. But that's part of the design effort that's up to you to figure out.

Now for say 720p 30Hz I think that's around a 37.125Mhz pixel clock. So data will come in over LVDS at about 297Mhz over LVDS for three lanes (back of the envelope could be off slightly here). Your HDMI clock would be half that at 148.5Mhz. So you might be able to count pixels with it. As you try to hit higher resolutions or frame rates that clock speed will go up.

  • \$\begingroup\$ Input clocks. I didn't know about that. Thank you. \$\endgroup\$
    – aalku
    Dec 5, 2017 at 15:00

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