# What is SNM(Static Noise Margin) in SRAM?

I have read multiple papers and articles about it but still, I am not able to understand fully. If you can explain me in layman terms I would be much happy. Thanks.

SNM can tell you a bit about the tolerance an SRAM cell has to noise before it risks loosing the 'memorized' bit.

SNM is a very simple measure with just one number, so it doesn't really tell you what kind of dynamic noise might flip the bit. But, since it's just one number it's easy to compare values and get a feel for when your SNM might land you in trouble.

There are actually three different SNM depending on what is being done with the SRAM cell:

• SNM_hold for hold (no operation)
• SNM_write for write operation

To find SNM_hold you consider two back-to-back inverters. If you draw both of their Vout(Vin) DC characteristic but swap the X/Y axes for the second, then you can find SNM graphically as the diagonal of the largest square that fits within the back-to-back DC characteristics. If the two inverters are not symmetric you must choose the smaller of the two possible squares for the SNM (one on each side of the cross-over point).

To find SNM by simulation you sweep a static noise voltage (DC source) one at each of the gate inputs as shown below. This paper (Seevinck et al. "Static-noise margin analysis of MOS SRAM cells" https://ieeexplore.ieee.org/document/1052809/ ) explains how you can get the largest diagonal using dependent sources.

simulate this circuit – Schematic created using CircuitLab

SNM_read and SNM_write are found same as SNM_hold except that you now load Vi and Vo with the transistors that are connected to the bitline. (You could include the access transistor leakage for SNM_hold but it's rarely relevant).

An SRAM is a very busy integrated circuit, with lots of surge currents flowing during the Read Cycle. There is magnetic field coupling, electric field coupling, and ground and VDD upsets. These totaled, degrade and reduce the static noise margin.

The read-comparator (perhaps sensing differential read lines) needs an accurate determination of what was the bit-cell (4T or 6T or 8T) state.

The coupling and upsets I mentioned are the causes of reduced confidence in that actual cell state.

• So what should be an ideal value of SNM in 6T transistor for 1V VDD. What happens when it is low and high? What can I do to my cell to have a good SNM value. Thanks. Commented Dec 6, 2017 at 4:51
• Do you have the math and physics to compute magnetic coupling? electric coupling? and I*R voltages in VDD and GND rails? Commented Dec 6, 2017 at 5:45
• Sorry I am not aware of those. Commented Dec 13, 2017 at 14:24