0
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My Code:

#include "../architecture/CMSIS/inc/stm32f4xx.h"

#define WAIT(x) for (int i = 0; i < (x); i++)

inline static void init_led2();

int main() {
  init_led2();                      // setup led3
  while (1) {
  #define INDEX 5
    GPIOA->BSRR = 1 << INDEX;       // set led2 output
    WAIT(0x1FFFF);                  // wait for awhile
    GPIOA->BSRR = 1 << INDEX << 16; // reset led3 output
    WAIT(0x1FFFF);
  #undef INDEX
  }
  return 0;
}


// led3 is connected to GPIO pin PB3
inline void init_led2() {
#define MASK 3                                // 2bit mask
#define INDEX 5                               // index of the port
  RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;                     // enable GPIOA clock
  // set the mode to general purpose output
  GPIOA->MODER &= ~(MASK << (INDEX * 2));     // clear bit field
  GPIOA->MODER |= 1 << (INDEX * 2);
  // set output mode to push-pull
  GPIOA->OTYPER &= ~(1 << (INDEX));
  // set low speed
  GPIOA->OSPEEDR &= ~(MASK << (INDEX * 2));
  // no pull up/down resistors
  GPIOA->PUPDR &= ~(MASK << (INDEX * 2));
#undef MASK
#undef INDEX
}

when i use make program with my makefile that uses openocd to program the board via st-link2 it seems to work fine. I get ** Programming Finished ** and it verifies correctly as well.

But the LED on my nucleo board is not blinking! I can't even get it to turn on if i comment out the reset line. What am i doing wrong?

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16
  • 1
    \$\begingroup\$ what you are doing wrong, is not describing what is happening when you run the program. \$\endgroup\$
    – jsotola
    Dec 6 '17 at 6:54
  • 1
    \$\begingroup\$ I do not have enough rep to comment but where is your clock configuration?? \$\endgroup\$
    – charansai
    Dec 6 '17 at 7:19
  • 1
    \$\begingroup\$ @charansai doesnt need one powers up with a default internal clock. \$\endgroup\$
    – old_timer
    Dec 6 '17 at 10:50
  • \$\begingroup\$ put parens around the 1 << index << 16 for readability/clarity. a disassembly would tell the whole story. need volatile int in the wait loop. dont think you have to mess with ospeed or or pupdir, but okay so long as you get the shifts right. your comment says PB3 but your code is messing with PA3 is it PA3 or PB3? \$\endgroup\$
    – old_timer
    Dec 6 '17 at 10:56
  • \$\begingroup\$ or actually your code is PA5 not PA3 nor PB3... \$\endgroup\$
    – old_timer
    Dec 6 '17 at 10:57
0
\$\begingroup\$

same family of card/chip. and this code works (this exact binary should work on your board/chip)

void PUT32 ( unsigned int, unsigned int );
unsigned int GET32 ( unsigned int );
void dummy ( unsigned int );

#define RCCBASE 0x40023800
#define RCC_AHB1ENR (RCCBASE+0x30)

#define GPIOABASE 0x40020000
#define GPIOA_MODER     (GPIOABASE+0x00)
#define GPIOA_OTYPER    (GPIOABASE+0x04)
#define GPIOA_BSRR      (GPIOABASE+0x18)

int notmain ( void )
{
    unsigned int ra;
    unsigned int rx;

    ra=GET32(RCC_AHB1ENR);
    ra|=1<<0; //enable GPIOA
    PUT32(RCC_AHB1ENR,ra);

    ra=GET32(GPIOA_MODER);
    ra&=~(3<<10); //PA5
    ra|=1<<10; //PA5
    PUT32(GPIOA_MODER,ra);
    //OTYPER
    ra=GET32(GPIOA_OTYPER);
    ra&=~(1<<5); //PA5
    PUT32(GPIOA_OTYPER,ra);

    for(rx=0;;rx++)
    {
        PUT32(GPIOA_BSRR,((1<<5)<<0));
        for(ra=0;ra<200000;ra++) dummy(ra);
        PUT32(GPIOA_BSRR,((1<<5)<<16));
        for(ra=0;ra<200000;ra++) dummy(ra);
    }
    return(0);
}


Disassembly of section .text:

08000000 <_start>:
 8000000:   20001000    andcs   r1, r0, r0
 8000004:   08000041    stmdaeq r0, {r0, r6}
 8000008:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 800000c:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000010:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000014:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000018:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 800001c:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000020:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000024:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000028:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 800002c:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000030:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000034:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000038:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 800003c:   08000047    stmdaeq r0, {r0, r1, r2, r6}

08000040 <reset>:
 8000040:   f000 f80a   bl  8000058 <notmain>
 8000044:   e7ff        b.n 8000046 <hang>

08000046 <hang>:
 8000046:   e7fe        b.n 8000046 <hang>

08000048 <PUT16>:
 8000048:   8001        strh    r1, [r0, #0]
 800004a:   4770        bx  lr

0800004c <PUT32>:
 800004c:   6001        str r1, [r0, #0]
 800004e:   4770        bx  lr

08000050 <GET32>:
 8000050:   6800        ldr r0, [r0, #0]
 8000052:   4770        bx  lr

08000054 <dummy>:
 8000054:   4770        bx  lr
 8000056:   46c0        nop         ; (mov r8, r8)

08000058 <notmain>:
 8000058:   b538        push    {r3, r4, r5, lr}
 800005a:   481b        ldr r0, [pc, #108]  ; (80000c8 <notmain+0x70>)
 800005c:   f7ff fff8   bl  8000050 <GET32>
 8000060:   2301        movs    r3, #1
 8000062:   1c01        adds    r1, r0, #0
 8000064:   4818        ldr r0, [pc, #96]   ; (80000c8 <notmain+0x70>)
 8000066:   4319        orrs    r1, r3
 8000068:   f7ff fff0   bl  800004c <PUT32>
 800006c:   4817        ldr r0, [pc, #92]   ; (80000cc <notmain+0x74>)
 800006e:   f7ff ffef   bl  8000050 <GET32>
 8000072:   2180        movs    r1, #128    ; 0x80
 8000074:   4b16        ldr r3, [pc, #88]   ; (80000d0 <notmain+0x78>)
 8000076:   00c9        lsls    r1, r1, #3
 8000078:   4018        ands    r0, r3
 800007a:   4301        orrs    r1, r0
 800007c:   4813        ldr r0, [pc, #76]   ; (80000cc <notmain+0x74>)
 800007e:   f7ff ffe5   bl  800004c <PUT32>
 8000082:   4814        ldr r0, [pc, #80]   ; (80000d4 <notmain+0x7c>)
 8000084:   f7ff ffe4   bl  8000050 <GET32>
 8000088:   2320        movs    r3, #32
 800008a:   1c01        adds    r1, r0, #0
 800008c:   4811        ldr r0, [pc, #68]   ; (80000d4 <notmain+0x7c>)
 800008e:   4399        bics    r1, r3
 8000090:   f7ff ffdc   bl  800004c <PUT32>
 8000094:   4810        ldr r0, [pc, #64]   ; (80000d8 <notmain+0x80>)
 8000096:   2120        movs    r1, #32
 8000098:   f7ff ffd8   bl  800004c <PUT32>
 800009c:   2400        movs    r4, #0
 800009e:   4d0f        ldr r5, [pc, #60]   ; (80000dc <notmain+0x84>)
 80000a0:   1c20        adds    r0, r4, #0
 80000a2:   3401        adds    r4, #1
 80000a4:   f7ff ffd6   bl  8000054 <dummy>
 80000a8:   42ac        cmp r4, r5
 80000aa:   d1f9        bne.n   80000a0 <notmain+0x48>
 80000ac:   2180        movs    r1, #128    ; 0x80
 80000ae:   480a        ldr r0, [pc, #40]   ; (80000d8 <notmain+0x80>)
 80000b0:   0389        lsls    r1, r1, #14
 80000b2:   f7ff ffcb   bl  800004c <PUT32>
 80000b6:   2400        movs    r4, #0
 80000b8:   4d08        ldr r5, [pc, #32]   ; (80000dc <notmain+0x84>)
 80000ba:   1c20        adds    r0, r4, #0
 80000bc:   3401        adds    r4, #1
 80000be:   f7ff ffc9   bl  8000054 <dummy>
 80000c2:   42ac        cmp r4, r5
 80000c4:   d1f9        bne.n   80000ba <notmain+0x62>
 80000c6:   e7e5        b.n 8000094 <notmain+0x3c>
 80000c8:   40023830    andmi   r3, r2, r0, lsr r8
 80000cc:   40020000    andmi   r0, r2, r0
 80000d0:   fffff3ff            ; <UNDEFINED> instruction: 0xfffff3ff
 80000d4:   40020004    andmi   r0, r2, r4
 80000d8:   40020018    andmi   r0, r2, r8, lsl r0
 80000dc:   00030d40    andeq   r0, r3, r0, asr #26
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3
  • \$\begingroup\$ cant really post this in a comment, can delete after read. \$\endgroup\$
    – old_timer
    Dec 7 '17 at 2:33
  • \$\begingroup\$ Can you move to chat? I want to send you a zip of my codebase so you can tell me where i'm screwing up exactly. \$\endgroup\$ Dec 7 '17 at 2:33
  • \$\begingroup\$ it might be a problem with my boot.o and init.o files that get linked in \$\endgroup\$ Dec 7 '17 at 2:34

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