I need to take exactly 200 Samples per 50Hz whereas the samples do not vary in phase. Thus, I thought about using a zero-cross detector and a PLL. The ADC is a sigma-delta ADC with an oversampling rate of 256. Therefore, the required clock is 2_560_000 Hz for driving the ADC.

The CS2000-C from Cirrus Logic seems to fit that purpose but is quite expensive. Does anyone have a cheaper solution to that problem?

  • \$\begingroup\$ What's so special with the CS2000 that you want to use it? Why not any old PLL? This is a pretty common use case for a PLL I think. \$\endgroup\$
    – pipe
    Dec 6, 2017 at 11:55
  • \$\begingroup\$ How much sampling-time-wander will you tolerate? 1picosecond is not practical. And with a 50Hz reference having lotta trash on the waveform, I doubt even 1 nanosecond or even 1uS is achievable. What are your jitter needs? \$\endgroup\$ Dec 7, 2017 at 3:53
  • \$\begingroup\$ My jitter needs are hard to determine. Anyway as I sample with 10kHz the waveform, I would say better than 5us. But the ADC itself is driven with the multiple of 10kHz due to its sigma-delta structure. As it propagates, this would be 5/256us ... which is quite hard. \$\endgroup\$ Dec 7, 2017 at 7:46

1 Answer 1


I suppose the 50Hz comes from mains. Since mains is rather noisy, the zero crossing point will most likely have substantial phase jitter. It would be better to use the entire wave and run that through a phase detector. Since you are already sampling the waveform, you can easily multiply it with I and Q sine waves in software, this will give you a much more accurate phase estimate. It also gets rid of the zero cross detection circuit.

Now, the PLL. Since you will most likely average several periods and use a low cut-off lowpass filter to extract phase and get rid of noise, you need a PLL with low drift over rather long time spans. Your XO-controlled PLL offers this...

However there is a much simpler way. You could simply run your ADC on a local XO clock, oversample a bit more (say, 40ksps instead of 10ksps) and do everything in software.

Basically you'd keep a phase counter (a kind of software PLL). Said phase counter is updated according to the phase detection done in software. Then use interpolation to resample the signal into what you want (ie, 200 samples per period).

  • \$\begingroup\$ A numerically-controlled oscillator is another option rather than PLL. Some made by SiliconLabs. But your re-sampled idea with fixed, stable oscillator is more elegant. \$\endgroup\$
    – glen_geek
    Dec 6, 2017 at 15:19
  • \$\begingroup\$ @peufeu thank you for your thoughts. Anyway, what do you mean exactly with XO-controlled PLL? The idea of resampling in software we do right now. But right now, it is not real-time as the dsPIC33 is not powerful enough. Therefore I try to make it in hardware and reducing the cost of the ADC. The phase detection instead of zero crossing is a good idea but anyway I need to find a way to trigger some external cheap pll. Any idea for that? \$\endgroup\$ Dec 6, 2017 at 19:10
  • \$\begingroup\$ The Cirrus chip is interesting, I think it will do what you want (I didn't test it of course, so cant be sure) ; it is a bit expensive though. "XO-controlled PLL" => In a regular PLL the oscillator would be a VCO, and this would drift a lot over one 50Hz period. In this chip it is a Fractional-N PLL clock synthetizer which can hold a fractional ratio relative to local XO without drift (in other words, it is a digitally controlled oscillator), and this is controlled by a digital PLL to follow the input clock... It's quite clever. \$\endgroup\$
    – bobflux
    Dec 6, 2017 at 20:00

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