# Design a T flip flop in VHDL using Modelsim, signal values not changing as expected

I was trying to design a TFF in VHDL. I wrote the code below

library ieee;
use ieee.std_logic_1164.all;

entity TFF is
port(
T: in std_logic;
clk: in std_logic;
Q, Qn: out std_logic
);
end entity;

architecture behavior of TFF is
signal q_state: std_logic := '0';
begin
process(clk)
begin
if clk'event and clk = '1' then
if T = '1' then
Qn <= q_state;
q_state <= not q_state;
Q <= q_state;
end if;
end if;
end process;
end behavior;


Then I used Modelsim to simulate the code. While testing I noticed that Q and Qn are the same. I wonder why this happend.

• It's clocked logic. There isn't an order like in C. If T=1 and there is a positive clk edge than those 3 things happen simultaneously. – ACD Dec 6 '17 at 19:13
• I thought the code in process part will run sequentially. isn't it like that? – Farbod Shahinfar Dec 6 '17 at 19:15
• Because signal assignment semantics. stackoverflow.com/questions/13954193/… As an experiment, try making q_state a variable, local to the process... – Brian Drummond Dec 6 '17 at 19:52

q_state <= not q_state;

Q <= q_state;

You coded this, assuming that q_state is complemented immediately and it will be assigned to Q. But actually in VHDL, all signals are scheduled to be updated only at the end of the process (known as delta delay), and the changes will be reflected only in the next process execution or simulation cycle.

Here q_state was 0 initially. q_state <= not q_state statement schedules q_state to be 1 for the next simulation cycle. Current value remains at 0 itself. So when Q <= q_state is executed, 0 is copied to Q, not 1. In the next clock edge, new value of q_state is available. Now if you analyze, you can see that both Q and Qn will continue to hold the same value in every clock cycle.

• You can use variables, if you really want these kinda immediate assignments somewhere in the code. :-) – Mitu Raj Dec 7 '17 at 20:08

A simpler and more direct implementation would be:

library ieee;
use ieee.std_logic_1164.all;

entity TFF is
port(
CLK     : in  std_logic;
RST     : in  std_logic;
T       : in  std_logic;
Q       : out std_logic;
Q_N     : out std_logic
);
end entity TFF;

architecture behaviour of TFF is

signal tState      : std_logic;

begin

pFlipFlop : process(RST, CLK) is
begin
if (RST = '1') then
tState  <=  '0';

elsif (CLK'event and CLK = '1') then

if (T = '1') then
tState  <=  not tState;
end if;

end if;

end process pFlipFlop;

Q    <=      tState;
Q_N  <=  not tState;

end behaviour;


but this introduces a delta delay onto Q_N which may be a problem if this feeds another CLKed flip-flop input.

Alternatively, you could use the below but it may implement more than one flip-flop, though synthesis optimisation should reduce it to one.

library ieee;
use ieee.std_logic_1164.all;

entity TFF is
port(
CLK     : in  std_logic;
RST     : in  std_logic;
T       : in  std_logic;
Q       : out std_logic;
Q_N     : out std_logic
);
end entity TFF;

architecture behaviour of TFF is

signal tState      : std_logic;

begin

pFlipFlop : process(RST, CLK) is
begin
if (RST = '1') then
tState  <=  '1';
Q       <=  '0';
Q_N     <=  '1';

elsif (CLK'event and CLK = '1') then

if (T = '1') then
tState  <=  not tState;
Q       <=      tState;
Q_N     <=  not tState;
end if;

end if;

end process pFlipFlop;

end behaviour;

• Both your examples are missing declarations for tState and qState. The identifier t may not be used in a signal declaration, it is a port of mode in. – user8352 Dec 6 '17 at 20:51
• As I imagine you noticed @user8352, it was a typo' calling the signal 't', not 'tState' as intended. Thanks for calling it, fixed now :-) – TonyM Dec 6 '17 at 21:10
• And what of qState? – user8352 Dec 6 '17 at 22:01