# Poor man's clock MUX with an LVDS input

I want to send two different 10MHz clock signals to a device. My board have tight volume and power constraints and I would rather not use a complicated clock buffer/PLL/MUX IC.

The first source have a low period jitter, below 10ps. The second source jitter is less important.

I came up with a circuit that could eliminate the need for a MUX:

simulate this circuit – Schematic created using CircuitLab

Only one of the source is enabled at any time.

The device with the LVDS input is a TDC-GPX2. The LVDS input common mode is limited from $V_{ID}/2$ to $2.2V - V_{ID}/2$ where $V_{ID}$ is the differential input voltage. $V_{ID}$ must be higher than $0.2V$.

Is there a problem with that circuit? Could it degrade my clock signal significantly, by adding several picoseconds of jitter?