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I want to send two different 10MHz clock signals to a device. My board have tight volume and power constraints and I would rather not use a complicated clock buffer/PLL/MUX IC.

The first source have a low period jitter, below 10ps. The second source jitter is less important.

I came up with a circuit that could eliminate the need for a MUX:

schematic

simulate this circuit – Schematic created using CircuitLab

Only one of the source is enabled at any time.

The device with the LVDS input is a TDC-GPX2. The LVDS input common mode is limited from \$V_{ID}/2\$ to \$2.2V - V_{ID}/2\$ where \$V_{ID}\$ is the differential input voltage. \$V_{ID}\$ must be higher than \$0.2V\$.

Is there a problem with that circuit? Could it degrade my clock signal significantly, by adding several picoseconds of jitter?

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As I read the specs, even a controlled bipolar switched 3.5mA current source into a 100 Ω Differential load on clock will add 4ps (p-p) of INL jitter to subsequent clocks generated.

Now the LVDS expects 350mV diff. input from 100 Ω so use a 1.8V 25 Ω CMOS switch voltage source with +/-25% tolerance (est.) on RdsOn Pch/Nch may have skew but significantly more ringing without a load from Z mismatch depending if the prop. delay on the path is greater than 10% of the rise time from inherent load capacitance. This may reduce your false trigger voltage margin with a return loss near 0 dB. Therefore without a balanced differential signal, signal integrity may be worse from crosstalk to nearby output signals due to the unbalanced drive.

But without knowing your crosstalk or mutual coupling or stripline layout, added jitter may be hard to estimate. But keep in mind the datasheet for a t_Stop2-1 is 94.4ns with the 6 sigma jitter of about 10ps. but I would not eliminate the differential load if you can Gate the driver input, but that may cause other latency issues.

Just a SWAG, but differential CML or current mode logic is best for any jitter sensitive logic and use CoG caps to avoid microphonic jitter.

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  • \$\begingroup\$ Thanks. Could you clarify your answer: What is INL Jitter? What is the implication of the first paragraph? Those this mean that all clocks signal using LVDS have a minimum jitter of a few ps? Or is this added jitter? Note that there is no internal termination, so I can set the impedance if needed. The rise time is in the few nanosecond range, I am not worried about ringing. What is t_Stop2-1? I believe that the precision is rather around 10ps for 1sigma on this device, not 6 sigma. If I keep the differential load, wouldn't the signal travel back to the other buffer? \$\endgroup\$ – pserra Dec 6 '17 at 23:35
  • \$\begingroup\$ Fig 22 INL Integral Non-Linearity to programmed output added jitter from an ideal 20MHz clock input with 0 jitter with ideal source connections. Stop results Fig 11, 19,20,21 \$\endgroup\$ – Sunnyskyguy EE75 Dec 7 '17 at 0:09
  • \$\begingroup\$ Ok. The input I want to connect the two clock to is REFCLK input, so figure 22 could be relevant. But the Integral non linearity is characteristic of the converter itself, I don't see how that relate to jitter at the input. My understanding of it is that it's more a measurement of the accuracy of the converter when jitter is as low possible. \$\endgroup\$ – pserra Dec 7 '17 at 0:28
  • \$\begingroup\$ correct. So input jitter occurs when synchronous stray noise adds or subtracts to the slew rate of the input signal, (noise sum PM -jitter) which is why I mentioned crosstalk and high impedance. Also supply decoupling is important for ground or supply shift. So if Rise time is 4ns and desired jitter is 4ps then that synchronous noise if it exists must be 60 dB down. Or if Vcc changes and it is AC coupled, the average DC level will affect the jitter from Vss ripple. \$\endgroup\$ – Sunnyskyguy EE75 Dec 7 '17 at 1:30

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