# Improvements to 7-segment decoder

I am just learning to build circuits, and I thought I would try my hand at building a 7 segment decoder using just logic gates.

I drew the following schematic in Logisim, and it works, but there are a lot of chips to implement. I don't have a source for a 13 input OR gate, so it will turn into more chips than the logic diagram shown here.

Q: Can you point me to any tricks that will reduce the gate/transistor count?

• google karnaugh maps ... you need to draw 7 maps, each one having 4 inputs – jsotola Dec 7 '17 at 3:12
• you can also use seven de-multiplexers each with 4 inputs – jsotola Dec 7 '17 at 3:14
• Just to follow up a little on @jsotola said. Anything that needs to be logically reduced can be done using K-Maps. It's literally the answer to every question with regards to logical reduction and rearrangement... okay fine. Maybe some DeMorgan's Theorems can help too. – KingDuken Dec 7 '17 at 3:28
• You could do it the lazy way and look at datasheets for commercial decoders. You should decide whether you want to decode 0..9 or 0..F, and whether the 9 and 6 will have tails or not (though the tails are necessary to distinguish b from 6 if you decode 0..F so there are really only 3 viable choices rather than 4). – Spehro Pefhany Dec 7 '17 at 3:58
• Just a quick look... Are you sure you are getting the right result for zero with the above circuit? – R Drast Dec 7 '17 at 10:09

The "simplest" optimization you can do is using karnaugh maps as jsotola commented. This reduces your circuit a lot. But you can do more. The gates used for A might have terms that B has too. The karnaugh maps have multiple optimal results and by picking the right combintion of results you can increase the amount of shared terms.
You can also use more types of gates than the standard sum-of-products or products-of-sum solutions from karnaugh maps. I found that XOR gates are often helpful in reducing the gate count.