The "simplest" optimization you can do is using
karnaugh maps as jsotola commented. This reduces your circuit a lot. But you can do more. The gates used for A might have terms that B has too. The
karnaugh maps have multiple optimal results and by picking the right combintion of results you can increase the amount of shared terms.
You can also use more types of gates than the standard sum-of-products or products-of-sum solutions from
karnaugh maps. I found that XOR gates are often helpful in reducing the gate count.
As for your 13 input or gate: You can build one yourself by simply connecting each of the 13 inputs to a diode and connect all the outputs. You will loose some voltage across the diodes so your output HIGH level might be lower than you like. Connecting 2 NOT gates in series can restore the level to proper HIGH. That uses less gates than using multiple OR gates to reach 13 inputs overall. But after optimizing you shouldn't need such a large OR gate.
You can also look at the solution I found for my binary to 7 segment HEX decoder. I managed to optimize it down to 24 gates in 6 ICs.