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I am using an FPGA vhdl UART code to send 16bits of data with a 1 start bit, 1 stop bits and even parity bit. I need to check whether the sent 16bit packets are correctly receiving using a terminal software on windows pc. I did a research on google and found many terminals that only allow for 8 bits of data with parity check + start + stop bits, in my case its 16 bits. so how can I monitor this 16 bits of data using a terminal?

Updated,

I have performed something like this (pseudo-code) and did not work

X_16_bit --> 16 bit data X_16_bit --> AB

A ---> upper 8 bits

B ---> lower 8 bits

this 16-bit X_16_bit updates at every 0.5 seconds. in a 50MHz clocked process, in the same process, I do below operation. (did not work)

x <= 0; and y <= 0; are initialized as varibles inside below process

process(clk_50)
variable x  : STD_LOGIC:= '0';
variable y  : STD_LOGIC;
variable A  : std_logic_vector(7 downto 0)              := x"00";
variable B  : std_logic_vector(7 downto 0)              := x"00";
variable X_16_bit   : std_logic_vector(15 downto 0)             := x"0000";

begin

                  ------------------------
***THE CODE THAT calculates X_16_bit at every 0.5 seconds*** 
                   -----------------------

//SPLITTING code runs in 50MhZ clocked process 

if (x ='0'){ // stop A and B is being mixing with a new value
 A :=  X_16_bit(15 downto 8);
 B :=  X_16_bit(7 downto 0);
}

if (x='0'){ // 1stly send upper 8 bits
  tx_data <= A;
  y:=1;
  x:=1;
}
if (y='0'){ // 2ndly send lower 8 bits 
  tx_data <= B;
  x:=0;
}
y:='0';
end process;

the below error was solved, tx_data is a signal that used to transmit data in tx transmitter process i got error

 Error (10028): Can't resolve multiple constant drivers for tx_data

UART transmitter is another process I use baud rate 19200 even parity the VHDL I have used is in this link

UPDATED

process(clk_50)
variable x  : STD_LOGIC:= '0';
variable y  : STD_LOGIC;
variable A  : std_logic_vector(7 downto 0)              := x"00";
variable B  : std_logic_vector(7 downto 0)              := x"00";
variable X_16_bit   : std_logic_vector(15 downto 0)             := x"0000";

begin

                  ------------------------
***THE CODE THAT calculates X_16_bit at every 0.5 seconds*** 
                   -----------------------

//SPLITTING code runs in 50MhZ clocked process 

UPDATED

        X_16_bit := x"4563";
        IF(x = '0') THEN     
            A := X_16_bit (15 downto 8);                        
            B := X_16_bit (7 downto 0);
            tx_data <= A;   
            x := '1';

        ELSIF(x = '1') THEN 
            tx_data <= B;                       
            x := '0';
        END IF;
end process;

UPDATED with this code i get only 63 on tx output. i dont get 45 at all.

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  • \$\begingroup\$ Put something in the middle that splits it. \$\endgroup\$ – Ignacio Vazquez-Abrams Dec 7 '17 at 4:12
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    \$\begingroup\$ How's your code doing? The error probably comes, because x and y can be 0 at the same time. When this happens you would be assigning A and B to tx_data. Check your assignment for y. If you aren't doing anything with x, you can discard y and check for x = '0' then tx_data <= A elsif x = '1' then tx_data <= B and an else. \$\endgroup\$ – Eggi Dec 7 '17 at 7:08
  • \$\begingroup\$ @Eggi thank you that error was solved with your help \$\endgroup\$ – oppo Dec 7 '17 at 8:25
  • \$\begingroup\$ @Eggi i have updated the code can you check? \$\endgroup\$ – oppo Dec 7 '17 at 9:32
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    \$\begingroup\$ The problem with your code is: You want the process to process when there is a new rising edge, have a look at some process tutorials. Also, variables are a bit tricky when synthesized. I would recommend to start with simple Signals and discard the variables for now. The code looks bad in a few ways. You are assigning a value to A and reading from A at the same time. You are aware that the old value from A is read before the new value is assigned? \$\endgroup\$ – Eggi Dec 7 '17 at 9:39
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The basic answer is that you can’t. At least not with the format you are using.

To use an existing terminal you need to conform to a standard data type. That is 7 or 8 bits of data with or without parity with one or more stop bits and one start bit. That is a minimum of two 9 or 10 bit characters. For either 18, 20, or 22 bits in total. This in must cases will be a hardware limitation.

You are sending 19 bits: start bit, 16 data bits, parity bit, and a stop bit.

The best you can do, is set the terminal to 8 bits of data and no parity, and expect the terminal software to ignore framing errors. But even then two data bits will be interpreted as a start bit and a stop bit. If your data is not zero in that position the framing will be off.

Some PC USARTs might be able to handle non-standard serial formats such as yours. But using that capability is very likely to require writing your own low-level driver.

You can interpose some hardware with a compatible USART that can handle your data format, and parses it into two separate 8-bit standard characters to send to the PC.

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Unfortunately the code snippet you provided does not provide enough information to enable me to give you definitive answer. We do not know what A,B,X, or Y represent. Also your VHDL has a number of issues. 1) You have CLK_50 in you process sensitivity list, but you never reference that signal. 2) It looks like you are writing C type code that is sequential, rather than VHDL code. All the VHLD code will be executed each time that clock signal changes, whether low to high or high to low. Signals will only get values that are last assigned in a process.

Putting that aside, your UART cannot accept new data until your code verifies that the UART is ready to accept 2nd character. You must check the TX_READY signal of the UART before sending another character.

Good luck.

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  • \$\begingroup\$ x and y are variables defined in the process used as flags to keep track of two 8 bits data. \$\endgroup\$ – oppo Dec 7 '17 at 5:23
  • \$\begingroup\$ I rewrote my answer after I read the interface specification for your UART \$\endgroup\$ – Paul S Dec 7 '17 at 5:35
  • \$\begingroup\$ I see A and B and x and y in your process, but I do not see if they are signals, or variables, or inputs to another component. Can you include those definitions? \$\endgroup\$ – Paul S Dec 7 '17 at 5:41

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