Edit: I have been able to achieve 560ps uncertainty in simulation by using external PLL feedback through the entire chip. Once I verify in real hardware I will post a complete solution.
I'm trying to synchronize the outputs of two physically separated Spartan-6 FPGAs. Ideally, the skew between the two device's outputs would be less than 1ns.
The outputs are differential pins controlled by an OSERDES2.
One possibility might be to distribute a reference clock to the two FPGAs. The signal would be routed so that it arrives at each FPGA at "exactly the same" time.
The reference clock would be passed through a PLL, with feedback through a BUFIO2_FB device. As shown in the clocking resources example:
Will this feedback mechanism cancel out clock insertion delay, so that the IOCLK is in phase with clock input pin?
The ISERDES2 in the same IOCLK domain would register a reference data signal which simply denotes a particular clock edge to align the output with.
Are there other device variations which will prevent the outputs from being deterministically in phase?
For example I'm concerned the propagation delay from OSERDES2 to output pin could vary greatly between devices. Based on timing datasheet:
Does this specification of 0.94 ns mean that the propagation can be anywhere from 0 to 0.94ns across different devices?
Is there any more sound approach to this problem?