# Is there an advantage to my sequential circuit optimization?

I'm trying to create a snake game on a Xilinx Artix7 FPGA, and one of the things I want to check is if the snake has collided with itself. I need to perform this check between game updates to know by the next update whether the game has ended.

The snake in my game is made up of discrete segments, so to check if the snake has collided with itself, I just check if the first segment (the head) overlaps with either the second, the third, the fourth, etc. My plan is to do this sequentially with a clock much faster than the game clock.

The thing is I think I can get away with only checking if the head collides with every other segment. However, is there really any advantage gained by this "optimization"?

The game, if running at say 50 FPS, would have an update period 20 ms. The clock the Basys3 board supports is 100 Mhz which is a period of 10 ns. This means that in the interval between updates for the game, I can go through 2 million segments, which is far more than the snake could ever have. Since the game doesn't really need to get faster than 50 FPS, finding the answer twice as fast doesn't do anything because all I would do is just sit around and wait for the next update.

Another thing I thought of was maybe I could configure the create_clock command in my XDC (constraints) file to be slower, but is there an advantage to doing so? Does it consume less power or something?

The last thing I could think of is if I used a combinational version of collision checking like so

(head == seg1) || (head == seg 2) || (head == seg3) || ... || (head == segN)


With my optimization, it would only take half as much hardware, but still way more than the sequential version. Since it's combinational, the answer would be available almost instantly, but again, since I've got time to kill, I don't see an advantage there either.

Is this a useless optimization?