In the following circuit, my understanding is that when there is a spike or rise in the data line higher than Vcc, the top diode conducts and the voltage flows into the path to protect the downstream IC/circuitry.
There are "four quadrant" power supplies which can do what you're thinking they won't, but even if the supply is not such, the energy will go to charging the capacitance between Vcc and GND (both the power supply's output capacitor and the board's decoupling).
This is better than not having the protection because the energy of an ESD event is spread out so the voltage is much smaller at any point.
Vcc will be somewhat higher for a moment but this has little effect.
What you are missing are two things, (a) that the ESD spike is typically produced by a small capacitor (industrially-accepted "human body" model is 100pF) and therefore is short (100 ns typical), and (b) that any power supply rails have substantial bypass capacitors attached (at least 100,000 pF and much more). So in case of ESD spike the short-lasting charge gets easily "absorbed" by those capacitors without noticeable increase in Vcc.
In fact, the 0.1uF caps are strongly recommended to place in closest proximity to ESD protective diodes.
If you mean how to protect an input from long sustained overvoltage, then the signal path should have a sort of switchable voltage divider. An example would be this US patent, where a N-MOS transistor essentially disconnects the input when it goes above the gate threshold voltage.
The whole point of the ESD diodes/devices is to protect the internal circuit which is sitting in the TTL CMOS block in your figure. A spike in voltage at the I/O pad will necessary damage the gate oxides of the mosfets/transistors in the circuit path. To avoid that, the diodes act as a very low resistive path for voltages higher than Vcc and lower than Gnd. When the pad is driven with a voltage higher than Vcc the top diode conducts enormous current and fully protects the internal circuit as its look-in impedance is quite high compared to the diode paths. Same is the case when the pad has a negative voltage spike.
Most of the CMOS technology circuits have ggNMos based configurations as ESD protection which acts similar to the case above.