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In the following circuit, my understanding is that when there is a spike or rise in the data line higher than Vcc, the top diode conducts and the voltage flows into the path to protect the downstream IC/circuitry.

But how does that voltage flow into the top Vcc, which is a probably a power supply? Or am I missing something? enter image description here

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  • \$\begingroup\$ A "spike" and "sustained rise" are different things, and require different solutions. The structure shown is only good for short ESD spikes, provided that there is a good low-ESR bypass capacitor from Vcc to GND in near proximity to diodes. \$\endgroup\$ – Ale..chenski Dec 8 '17 at 19:03
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There are "four quadrant" power supplies which can do what you're thinking they won't, but even if the supply is not such, the energy will go to charging the capacitance between Vcc and GND (both the power supply's output capacitor and the board's decoupling).

This is better than not having the protection because the energy of an ESD event is spread out so the voltage is much smaller at any point.

Vcc will be somewhat higher for a moment but this has little effect.

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  • \$\begingroup\$ What if the over voltage is not momentary but constant for a long duration? Would that longer increase in Vcc cause issues somewhere else? \$\endgroup\$ – ohmmy Dec 8 '17 at 14:27
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    \$\begingroup\$ If the overvoltage is constant for a long duration, it is very unlikely to be caused by ESD. \$\endgroup\$ – Dampmaskin Dec 8 '17 at 15:12
  • \$\begingroup\$ Don't need a four quadrant supply as long as clamp current injected into Vcc rail is below the whole circuit current consumption. A simple KCL proves so far power supply is still sourcing current. \$\endgroup\$ – carloc Dec 8 '17 at 15:19
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What you are missing are two things, (a) that the ESD spike is typically produced by a small capacitor (industrially-accepted "human body" model is 100pF) and therefore is short (100 ns typical), and (b) that any power supply rails have substantial bypass capacitors attached (at least 100,000 pF and much more). So in case of ESD spike the short-lasting charge gets easily "absorbed" by those capacitors without noticeable increase in Vcc.

In fact, the 0.1uF caps are strongly recommended to place in closest proximity to ESD protective diodes.

If you mean how to protect an input from long sustained overvoltage, then the signal path should have a sort of switchable voltage divider. An example would be this US patent, where a N-MOS transistor essentially disconnects the input when it goes above the gate threshold voltage.

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  • \$\begingroup\$ Thanks I was under the impression this circuit would do both ESD and an over voltage event. Confusion came from used to seeing a TVS being used for ESD \$\endgroup\$ – ohmmy Dec 8 '17 at 19:08
  • \$\begingroup\$ @ohmmy, this circuit can be used to protect from overvoltage if you can afford a limiting resistor upfront, say, 200 Ohms, such that the input capacitance of your IC wouldn't degrade much of your signal edges. For signals under 10-30 MHz this shouldn't be a problem. \$\endgroup\$ – Ale..chenski Dec 8 '17 at 19:15
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The whole point of the ESD diodes/devices is to protect the internal circuit which is sitting in the TTL CMOS block in your figure. A spike in voltage at the I/O pad will necessary damage the gate oxides of the mosfets/transistors in the circuit path. To avoid that, the diodes act as a very low resistive path for voltages higher than Vcc and lower than Gnd. When the pad is driven with a voltage higher than Vcc the top diode conducts enormous current and fully protects the internal circuit as its look-in impedance is quite high compared to the diode paths. Same is the case when the pad has a negative voltage spike.

Most of the CMOS technology circuits have ggNMos based configurations as ESD protection which acts similar to the case above.

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  • \$\begingroup\$ Yes but what I was wondering is, when there is voltage on the I/O Port that is higher than Vcc, where does it go when the top diode conducts? It merely merged with existing Vcc voltage? Doesn’t that cause any issues since it’ll add to it? \$\endgroup\$ – ohmmy Dec 8 '17 at 18:10
  • \$\begingroup\$ Think of the Vcc source as a infinite supply of positive charges as it's a battery of good energy rating. Now, the spike you see on the pad will generally have a very small amount of energy since it occurs for a short duration of time. When this is the case, the Vcc source voltage is affected as you think, but the magnitude is very small because of the energy differences between them. \$\endgroup\$ – Aditya Madhusudhan Dec 8 '17 at 18:13
  • \$\begingroup\$ What about if it’s longer than a short amount of time? Like if it’s not just ESD but somehow an over voltage situation on the signal input? \$\endgroup\$ – ohmmy Dec 8 '17 at 18:15
  • \$\begingroup\$ @ohmmy, if there's a constant voltage higher than Vcc, then it's not to be considered as ESD event as it seems to be wrongly sourced from other source where the pad is not supposed to be sourced with a constant voltage higher than Vcc. \$\endgroup\$ – Aditya Madhusudhan Dec 8 '17 at 18:15
  • \$\begingroup\$ @ohmmy But, if the voltage at the pad is within the breakdown range of the circuit elements in CMOS block, I guess you can just think that there will be a constant leakage of current from the pad to Vcc which then depends on the specs of the I/o pad on how much current can be drawn etc. \$\endgroup\$ – Aditya Madhusudhan Dec 8 '17 at 18:18

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