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I feel that this is a stupid question but I have really no idea how to answer it.

Looking at this answer first part and of course the other answer it's pointing to, I understand that high frequency current loops should be kept on a local ground net.

But the first link I've put here suggest joining the ground of devices close to each other. While I understand that a ground net is a net and so should contain multiple devices, how to decide which devices belong to the same net ?

At first I though about distance, but then all the devices get connected together on a dense board. I also though about uniting devices that were close and had similar switching speeds, but on a synchronous system that thought doesn't work, so is there any rule of thumb about that ?

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You need to keep the total worst case summation of voltage upsets to be SMALLER than the logic-family noise margin.

I watched a guy use an early automatic place-and-route software tool, to implement a TTL IO expander card. The signal traces were minimal; I asked about the GND (twas only 1/16 inch wide), and was told by the logic/PCB designer there had been no problems using 1/16 inch in the past.

Of course, 10mA/10nS * 1uH inductance (1 meter of trace in air) produces

10mA / 10nS * 1uH = 1mA/nS * 1uH = 10^+6 amp/sec * 1-^-6 Henries, or ONE VOLT upset.

Couple years later, the logic/PCB guy having been killed in a plane crash, I got a phone call regarding occasional spurious resets of the MCU/IOexpander combo.

I simply said "Oh, yeah. I know that board. Replace the GND daisy chain with a GND plane."

I heard nothing more about the spurious resets.


To estimate inductance, I use 1nanoHenry per MilliMeter. Rather accurate for short wires; approx. 50% high for 1 meter lengths of thin wires.

This works for wires and traces over air (no plane within at least the wire diameter). Clearly twinleads and twistedpairs will have errors.

If the wire/trace is over a plane, reduce the inductance by 10:1. Of course this 10:1 depends upon ratios such as trace thickness (or wire diameter) to distance above the plane.

Notice any piece of metal can be a plane for some distance. Thus VDD or GND or just wide GND runs or wide VDD runs (or a large bypass cap) can serve as a "plane" for some distance.

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  • \$\begingroup\$ How can you estimate the amount of trace in the air versus in copper ? By looking at the return current's path ? \$\endgroup\$ Dec 10 '17 at 12:35
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You could estimate the xx nH + xx mOhm per via and reduction in ESL with transient noise from Ic=CdV/dt and V=LdI/dt and give a noise budget for supply and ground ripple and estimate spacing to < 5% wavelength, but we can only guess your application. So you should observe best practices in similar applications and decide what your PWB shop suggests for microvias.

This site is consistent with my thinking. http://www.interfacebus.com/Design_Capacitors.html

Keep decoupling cap close to each IC. 0.01uF per MSI IC for best immunity with direct connection to ground/Pwr plane for <=5V Logic. It depends on how many gates are being switched synchronously. SSI gate IC's can use fewer vias and decoupling caps but it depends on what noise margin specs you define.

So no explicit Rules can serve all applications.

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    \$\begingroup\$ My application is a only CMOS single-board 20 Mhz-ish device if that's of any help. \$\endgroup\$ Dec 9 '17 at 22:11
  • \$\begingroup\$ Not much. 3.3V or 5V? total curtent>? Any ADC? or analog? \$\endgroup\$ Dec 9 '17 at 22:15
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    \$\begingroup\$ 5v fully digital. Total current ranging from about 50 mA to 200 mA but I'd like to have this question as generic as possible. \$\endgroup\$ Dec 9 '17 at 22:17

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