The purpose of ESD (electrostatic discharge) impulse capacitor discharge tests is to simulate a static charged human finger and a metal cart on insulated wheels touching a conductive surface. These tests have various levels for acceptance criteria such as; no interference, no operator intervention and no damage. The arc is limited for the HBM model with 1.5k from 100 pF, which can generate 15A at 15kV.
Solution examine signal rise at various points inside on the MOBO by injecting 15A discharges from low voltage 10uF//0.1uF from low ESR caps fed by coax shield. Use Ohm's law to limit the 15A current using a calibrated low L resistance in order to obtain the fast rise time of 150ns.
How to make a low L low R value (or low ESR, low ESL wire?)
Say you want to inject 15A from AC gnd input to an earthed chassis. This by UL/IEC standards must be < 0.1 Ohm, so measure it by injecting 1Adc from some lab supply. Let's say, it is only 30 mOhms and you want to inject 15 A. at 1.5 Volt. Then measure your short coaxial cable braid or Litz wire that will be used to create a current ground pulse loop and make up the difference for 100m Ohm. You can also adjust coax length if you raise the voltage but don't raise the voltage too much to create ESD protection diode failures. If >1.5V then remove the 1mF cap. THe ESD protection diodes inside most CMOS are only rated for protection of 5mA dc or about 1 mJ or 4kV @ HBM.
Ideal HMD impulse
CV² = 3 mJ
RC = 150 ns
I = 15A ground loop from Power entry gnd to signal ground near fault
The effects are then monitored on the MOBO using a differential probe or 10:1 probe with clip and ground lead removed using only a short (1cm) ground wire stub (Resistor lead) to the probe coaxial barrel and probe pin tip to signal. Then examine inductance of all ground paths and crosstalk to nearby signals or ground shift. A shorted probe tip to barrel ought to be a zero signal at any ground when done right , while probe cable orientation also matters.
Choices of insulated standoffs and metal standoffs can make a different good or bad depending on current paths and proximity of signals. Using RF choke can raise the MOBO 0Vdc to earth ground impedance to RF while providing low impedance to AC currents from earth grounded monitors and earth grounded PSU line filters. But then good case shielding is mandatory for emissions without slots for radiation or egress on I/O cables. Thus large CM ferrite clamshells are molded onto all VGA cables.
TVS protection on the interface offers good clamping protection with some rise time limits. But this does not help attenuate ground return currents from coupling back into the motherboard 0V ground plane and I/O signals unless diverted carefully.
Remember that inductance is only controlled by length to width ratios for the conductor and the number of turns if any, so a square of any size has the same inductance whether it is 1mm or 1m and that shielding sensitive signals is common mode not differential adds capacitance. A CM choke raises CM impedance with some loss so that a shunt CM capacitance improves RF attenuation by 2nd order effects while a shield diverts external currents while protecting inner wires, but better if they are balanced differential signals. You may only need 10~20 dB attenuation depending on the test results at 10kV and 5kV but the root cause is first insulation breakdown followed by high current dI/dt. You can test dI/dt with low voltage cap discharge as above and then measure critical signals on IO chips.
Remember that all BSOD's in Windows are caused by incomplete kernel IO commands, so any disturbances that result in a "hung I/O" or unacknowledged kernel hardware interrupt will cause a BSOD. Only when User Mode H/W drivers were created could these BSOD's be eliminated at some performance cost to detect and recover from these events.
A sample of personal experience
I once had bathroom fan timer switch cause an arc that caused my video monitor and blink off for half a second just from the line glitch. But I have not had a BSOD since Win XP for many reasons. You can simulated radiated noise spikes easily using a small SPDT relay using the NC contacts to interrupt the coil current and using a twisted pair of wire with a hand-wound insulated coil at the end, use that current to break low current but very short release ionization arc time thus generate high dV/dt noise and high dI/dt near any sensitive equipment. A very effective buzzer and EMI test gen/ that will burn out quickly if you apply full coil voltage for radiated noise. Yet back in the early 80's our company made keyboards with exposed LED's and the breakdown gap in the LED access hole was small enough for an ESD failure, so all keyboards in the world since then tend to use a light pipe due to the 15kV can reach 5mm to 15mm sharp points.
In engineering terms, this requires an understanding of insulation breakdown, RF shielding, isolation, surge suppression and common mode rejection over a very wide electromagnetic spectrum. You expect this because that is the Fourier Spectrum of an impulse.
These tests were originally developed by companies such as my former employer in the 70's and early 80's ( including myself on our Corporate EMC Standards test committee) then standardized by various commercial and military groups then standardized by IEEE , JEDEC and now IEC 61000-4-2.
So naturally many different solutions have developed over this time.
A series of 20 consecutive discharges, of 10(+) and 10 (-) polarity with a 1 second intervals between pulses, constitutes the minimum ESD test sequence.
This leads into your next failure for EFT.
What's all this about a buzzer induced EFT
The EFT simulates everyday inductive switching with lower voltage and current levels. An EFT generator produces a 15 ms burst of 1kHz with a minimum of 33 bursts for a minute. ( like my AC fan timer glitch )
The most common failure mode is the coupling failure mode is the wide bandwidth of SMPS detecting the envelope of burst after the line filter and passing the signal thru the forward converter resulting in a DC overvoltage being detected or an over-reaction with undervoltage.
This can be simulated by using the same buzzer Relay to shunt an inductor carrying the Neutral AC current with a spare set of contacts (DPDT power relay) You can operate the relay at maybe 60% of Vdc coil voltage the inductor needs to carry the AC PSU current and it will generate a voltage according to LdI/dt, so the inductor does not need to be large. perhaps 10uH. Since it is only the Neutral side, you can safely calibrate the level to EFT failure threshold. Start with a low inductance loop and monitor DC glitches so your measurement methods are clean. This may required AC coupling to a 50 Ohm termination using coax to scope with a coaxial jack installed on the board or as above with 10:1 probe. If you can get a flat trace with 10mV/div with both in/gnd to ground then your scope capture is balanced. Otherwise you may get CM capture issues from probe CM ground lead inductance.
After you can simulate the and measure the effects on the DC voltages beign regulated you can determine what needs to be done. Typically only the 5V is used for negative feedback while the others are regulated by winding ratios and very high mutual coupling. So look for the Power OK signal and monitor each voltage for effects of EFT injected pulses.
Remember that you can inject pulses either by V= L * dI/dt or V= I * dL/dt. A pulse modulating relay contact shunted AC current inductor does the latter quite easily and you can adjust L to suit your AC current levels and measure V on neutral.
How to make a quick and dirty EFT generator
You can easily use another relay to gate the burst mode buzzer with a small duty cycle at a 8 Hz rate just like the EFT test driven from a signal pulse gen or a Schmitt Trigger inverter as an RC Astable clock with an added pull-down R on input to skew the output duty cycle from 50% to 5% of a 8Hz ( RC=30ms) to drive a transistor and drive a small relay to drive a 500~1kHz buzzer relay. ( Sound easy enuf?) (Sounds like a playing card pegged against your kiddy bicycle spokes.)
1st detect line filter DM noise then CM noise then DC output noise on 5V , 12V then MOBO regulated voltages then locate DC OK signal on MOBO. Once you can locate how the noise gets in and where, you have a much better idea on how to solve it. Which may include disqualifying the PSU supplier or the MOBO supplier if they cannot fix their problem, if it cannot be suppressed by the MOBO.
But you have to identify the specification that it does not meet for ripple noise input or output that causes the fault on the DC side then decide how to mitigate it by filtering. In some cases an additional CM choke with Y cap suppression to earth gnd may improve the isolation converting a differential pulse into a CM pulse which gets attenuated by the CM L and shunt C.