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In the polar transmitter, after the I and Q signals are converted to amplitude and phase, where the phase is in the range of -pi to pi, the phase is further differenciated to obtain the change in frequency and then fed to an ADPLL.

If the original samples contain a phase change from -pi+0.01 to pi-0.01, then there would be a change in frequency proportional to 2pi-0.02. Is there some way to limit the magnitude of this change? As the two samples are actually relatively close on the IQ-plane.

Another question is, if I wish to upsample the phase signal, the extended version of the type of phase change mentioned above creates an originally non-existent trajectory (as the interpolator does not know modular arithmatic). How should I solve this?

Thank you.

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This effect is a purely mathematical problem, caused by trying to do naive sums with phase. If you ignore a vital element of your domain, the \$2\pi\$ modularity, then you should not be surprised if sums that are too simple go wrong.

There are a number of solutions.

The first is to stay in the IQ domain, and calculate phase differences by \$IQ_n\times-IQ_{n-1}\$ (normalised by IQ power if that's not constant) instead of \$\phi_n - \phi_{n-1}\$. This involves several multiplies and adds instead of a single add, but you don't have the initial conversion from IQ to phase in the first place. This might be the best way to implement your upsampler.

The second is to note that in a properly operating system, the magnitude of the phase difference from sample to sample will always be less than \$\pi\$, so you can add an if/then to add or subtract \$2\pi\$ to each calculated phase difference if it's out of range.

MATLAB has a very handy function called unwrap(), which performs the second solution on a vector of naively calculated phase differences, to remove the phase jumps.

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  • \$\begingroup\$ In response to your 2nd suggestion: doesn't the ADPLL actually accumulates the phase differences from before to arrive at a new operating frequency for the DCO? Wouldn't changing the phase difference through modular arithmetic disrupt the operation of the ADPLL in some way? (Signal trajectory matters in my case, as I am using DPSK format modulation.) (1st suggestion increases the operating frequency of the CORDIC, not viable in my situation.) \$\endgroup\$ – user61665 Dec 11 '17 at 9:16
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Polar modulation is an odd choice here, you will tend to find that getting the AM and PM components to both match in frequency and phase response is way harder then you expect.

I would skin this slightly differently, stay in the cartesian domain and use a pair of carriers in quadrature together with two multipliers to perform the half complex (You only need the real component) multiplication directly. No modulation PLL required.

Two channels of CIC (plus short FIRs to clean up) to go from baseband to RF rate, a NCO running at the output or IF frequency outputting sine and cosine, and a half complex multiplier, job done?

A nice refinement if you can pull it off is to make the sample rate 4 times the output frequency, at which point the NCO and mixers basically go away because the NCO output for each of I,Q is either 1, 0 or -1 for every sample.

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  • \$\begingroup\$ The architecture has been set, cannot change it from my end. \$\endgroup\$ – user61665 Dec 11 '17 at 11:20

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