I am trying to synthesize a design in VHDL into a ProASIC3 FPGA using the Synplify Pro tool. The synthesis report gives me the following warning on inferred clocks.
@W:MT420 : | Found inferred clock counter_unit| pstate_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:bcu_ins.ctr_ins.pstate"
I traced back to the part of the code where the warning is being generated and the same is reproduced here for reference.
p_fsm_clk : process(reset_n_in, clk_25mhz_in) begin if (reset_n_in = '0') then pstate <= s0; elsif rising_edge(clk_25mhz_in) then pstate <= nstate; end if; end process p_fsm_clk; p_fsm : process(pstate,restart_ctr,enable_ctr2,sys_fail) begin start_ctr1 <= '0'; start_ctr2 <= '0'; case pstate is when s0 => --Reset state. All counters are reset if (sys_fail = '0' and restart_ctr = '1') then nstate <= s1; --move to start counter1 else nstate <= s0; end if; when s1 => start_ctr1 <= '1'; --Initiate counter1 if (restart_ctr = '1') then --restart the counters start_ctr1 <= '0'; --reset counter1 nstate <= s1; elsif (enable_ctr2 = '1') then --move to start counter2 nstate <= s2; else nstate <= s1; end if; when s2 => --Save the counter1 value and start counter2 start_ctr2 <= '1'; --assert flag to start counter2 if (restart_ctr = '1') then --restart the counters nstate <= s1; else nstate <= s3; end if; when s3 => start_ctr2 <= '1'; if (sys_fail = '1') then nstate <= s0; elsif (restart_ctr = '1') then --restart the counters nstate <= s1; else nstate <= s3; end if; when others => nstate <= s0; end case; end process p_fsm; --counter1 p_ctr1 : process(reset_n_in, clk_25mhz_in) begin if (reset_n_in = '0') then ctr1 <= 0; --value on reset elsif rising_edge(clk_25mhz_in) then if (start_ctr1 = '1') then --flag is asserted to start counter1 ctr1 <= ctr1 + 1; --increment counter else --flag de-asserted ctr1 <= 0; --reset the counter end if; end if; end process p_offset_cnt; --save the value of counter1 offset_val <= ctr1 when pstate = s2;
The logic contains two counters –
ctr2. The counters are run when there are no system failures. In the first phase
ctr1 is run, which is then followed by
ctr1 stops counting when
ctr2 is enabled. The value of
ctr1 determines how much later is
ctr2 started (in terms of 25MHz clock period), referred to as the offset. This offset value is stored to a signal vector, as can be seen in the last line of the code. The state
s2 is used for capturing the value of
ctr1 before it resets to 0.
offset_val <= ctr1 when pstate = s2;
I realised that this assignment statement is causing the inferred clock in the design (but don’t know why). When I put the same statement inside a clocked process, the inferred clock warning disappears. However, my logic doesn’t work correctly.
I am looking for a few clarifications in this regard.
- Why is there an inferred clock on pstate in this design?
- Is it alright to have such statements in the design? Does the presence of inferred clocks indicate a bad design practice?
- If it not ok to have inferred clocks in the design, how can I fix this by coding the logic differently?
- If it is ok to have inferred clocks, how can I let the tool know of it? What period constrain can I provide for such inferred clocks? How can I determine a meaningful period for such inferred clocks?