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I'm not able to write vhdl syntax. But for the exam we must be able to read and interpret it.

The essence of the code is

process{
  if(start) 
    c := 0;
  end if;

  if ( c )
     ...
     c := false;
   else
     c:= true;
     ....
 end if;

}

Assuming that c=1 (is a variable) in the beginning. I'm having difficulties interpreting what happens here

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Since the statements are inside a process they will execute sequentially just like software.

http://www.doulos.com/knowhow/vhdl_designers_guide/components_vs_processes/

If you have use ieee.std_logic_1164.all; and start is set to true or 1 elsewhere in the code, then if ( c ) would evaluate to false the else branch would be executed. Then c will be set to false and will retain that value until the next time this process executes (or some other process or combinatorial statement changes it).

If you don't have use ieee.std_logic_1164.all; the behavior is dependent on the compiler/synthesizer.

http://www.eda.org/vfv/hm/1153.html

There is a lot of code missing so I'm making a lot of assumptions here but hopefully you get the basic meaning.

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