Let's say we have the following code where
c are 3-bit wide representing unsigned numbers:
a <= (b + c);
Overflow is expected by the designer in this case. For example, if
c are equal to
3'd7 then expected result is
3'd6). The code itself is quite similar to that of a binary counter except that operands widths are greater than 1-bit.
The question is whether it is safe to assume that synthesis tools will create hardware that handles above case as expected by designer or should extra care be taken?