Let's say we have the following code where a, b and c are 3-bit wide representing unsigned numbers:

a <= (b + c);

Overflow is expected by the designer in this case. For example, if b and c are equal to 3'd7 then expected result is 3'd6). The code itself is quite similar to that of a binary counter except that operands widths are greater than 1-bit.

The question is whether it is safe to assume that synthesis tools will create hardware that handles above case as expected by designer or should extra care be taken?


Synthesis will give you a truncated but otherwise accurate result, assuming all regs/wires mentioned are unsigned (i.e. not declared with reg signed). The map tooling will probably warn about a 'carry' line having 'no load', if you can find it in the logs. You might be able to suppress the warning with an explicit bit select on the result or a mask:

a <= (b + c) & 0x7;

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