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I am measuring a voltage which looks something like the positive half of a sine wave and I want to drive the gate of a FET while this voltage is inbetween two certain points.

So for example the voltage has an amplitude of 10 V, the gate should go from low to high when the measured voltage reaches 1 V and turn low again when it reaches 6 V.

What is the easiest way to do that? I tried with a Schmitt trigger but could not get the gate to low again while still being on the rising edge of the measured voltage.

black line is the voltage I´m measuring, red line is the voltage I want to create

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  • \$\begingroup\$ HUH? You have three levels indicated. Your question is very unclear. Perhaps show a diagram indicating the waveforms and your required switching points. \$\endgroup\$ – Trevor_G Dec 13 '17 at 14:04
  • \$\begingroup\$ What supplies do you have? \$\endgroup\$ – Trevor_G Dec 13 '17 at 14:23
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    \$\begingroup\$ This sounds like a strange problem for anyone to have. There's a strong odor of XY problem. \$\endgroup\$ – Harry Svensson Dec 13 '17 at 14:23
  • \$\begingroup\$ Hi Trevor, you were right, the question was unclear, I added a picture to clarify what I want. The red line is the voltage I want to create. \$\endgroup\$ – Julian Dec 13 '17 at 14:27
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Perhaps you can use a window comparator along with a delayed signal slope comparator as shown below.

enter image description here

The top two comparators set your 1V to 6V range, the bottom one compares the input signal with a delayed version of the input. Depending on your frequency some adjustment to R4 and C1 may be required.

If all three conditions are met the output will be pulled high by R5.

I used LT1018s but LM339s will work just as well if your frequency is not too high. Comparators need to be open-collector or open-drain though.

enter image description here

HOWEVER

The issue with the above circuit is any noise in the signal can cause extra edges at the transition points 6V and 1V.

As such it is prudent to add some hysteresis.

enter image description here

Ultimately though, it would be better to use the edges separately to clock and reset a D-Type.

enter image description here

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    \$\begingroup\$ Wow thanks for the effort, this should work for me :) \$\endgroup\$ – Julian Dec 14 '17 at 10:20
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What you want is called a window comparator. Two comparators with open collector outputs tied together to one resistor to the positive rail. The low comparator goes high when the input is above 1 V. The high comparator goes low when the input is above 6 V. Between the two trip values, both comparator outputs are high so the output across the pull up resistor is high.

If the speed and precision are not extreme, an LM393 dual comparator (1/2 of an LM339 quad) is the classic part for this. The two trip points can be set with two independent voltage dividers of with one three-resistor string. Hysteresis is optional, depending on the application. Adding it keeps noise bursts out of the output, but shifts the trip points and makes the math a bit more complex.

Window comparator using LM339 - invert output

http://www.electronics-tutorials.ws/opamp/opamp107.gif?81223b

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    \$\begingroup\$ This does not do a rising edge... \$\endgroup\$ – Trevor_G Dec 13 '17 at 14:19
  • \$\begingroup\$ Hi AnalogKid, you may be right but it seems like a window comparator would give me an outputsignal on the falling edge of the measured voltage as well, is there a way to avoid that? \$\endgroup\$ – Julian Dec 13 '17 at 14:31
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    \$\begingroup\$ To avoid the falling edge pulse you also need some state, i.e. at least one flipflop. If you clock '1' into it on the rising edge of the Low comparator and clear it (Reset) whenever the High comparator is high, it should do what you need. \$\endgroup\$ – Brian Drummond Dec 13 '17 at 14:54
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    \$\begingroup\$ Trevor - yes, it does. Julian - The text of your question does not mention the falling edge restriction, and when I read it there was no graphic. As above, a third element of some kind is needed to manage that. \$\endgroup\$ – AnalogKid Dec 13 '17 at 16:22

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