I am working on an FPGA design in which I also have to integrate several legacy IP cores. I use asynchronous assertion and synchronous de-assertion for the master reset signal in my design.
I observed that some of the IPs I got use synchronous resets while the others use asynchronous resets.
Will this create any issues during design implementation?
Do I have to modify the IPs to use a common reset method or can I just ignore this? (I have some restrictions in modifying some of the IPs)