I am working on an FPGA design in which I also have to integrate several legacy IP cores. I use asynchronous assertion and synchronous de-assertion for the master reset signal in my design.
I observed that some of the IPs I got use synchronous resets while the others use asynchronous resets.

Will this create any issues during design implementation?
Do I have to modify the IPs to use a common reset method or can I just ignore this? (I have some restrictions in modifying some of the IPs)

  • \$\begingroup\$ You should not use async resets. If you have them in your design, make sure to synchronize them before connecting to a circuit with sync resets expectations. \$\endgroup\$ – Paebbels Dec 13 '17 at 23:59
  • \$\begingroup\$ I generally use async resets in the design. But I am making sure that the resets to the IPs are going through a reset synchroniser. However, by using two types of reset methodology in the design, will it cause issues in achieving time closure in the FPGA? \$\endgroup\$ – rvkrysh Dec 14 '17 at 15:15

If I have a design with synchronous reset, and you feed it with an async reset signal which may be asserted at any time, it internally goes via a clocked flip-flop. So for the design, it will be just like a synchronous reset. So it has to work.

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  • \$\begingroup\$ No, you can not connect a async reset to a circuit expecting sync resets!. You need to add a synchronizer circuit in between. You should not use async resets at all ... \$\endgroup\$ – Paebbels Dec 13 '17 at 23:58
  • \$\begingroup\$ What if the async reset is latched in Flip-flop in FPGAs ? The output of the flip-flop will be a synced reset I guess ?! \$\endgroup\$ – Mitu Raj Dec 14 '17 at 7:23
  • \$\begingroup\$ google.co.in/url?sa=t&source=web&rct=j&url=http://… -- check this . Since it will go through flip-flop in the synchronous reset design, async reset will work just as sync reset. \$\endgroup\$ – Mitu Raj Dec 14 '17 at 12:00
  • \$\begingroup\$ I think that's what a synchroniser circuit is meant to do, as suggested by @Paebbels. If I am right, it will also reduce the possibility of metastability. \$\endgroup\$ – rvkrysh Dec 14 '17 at 16:45
  • \$\begingroup\$ In FPGAs, I don't think you have to care about it, cz it would already be there on synchronous designs. Even if you implement a synchronous adder on FPGA, the input we give via switches on an FPGA board is like asynchronous. We can switch it anytime. But internally those inputs are sampled via flip-flop. Anyway, in the very first flip flop, there is always a chance of metastability. Check electronics.stackexchange.com/questions/234861/… \$\endgroup\$ – Mitu Raj Dec 14 '17 at 17:38

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