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Why is parity_value equal to value of 1 ?

check_parity verilog source code

parity_error

module check_parity(clk, serial_in, received_data, data_is_valid, is_parity_stage, rx_error); // even parity checker

input clk, serial_in, data_is_valid, is_parity_stage;
input [7:0] received_data;
output reg rx_error = 0; 

reg parity_value; // this is being computed from the received 8-bit data
reg parity_bit;  // this bit is received directly through UART

always @(posedge clk)
begin
    parity_value <= ^(received_data);
end

always @(posedge clk)
begin
    if (is_parity_stage)
        parity_bit <= serial_in;
end

always @(posedge clk)
begin
    if ((data_is_valid) && (parity_bit != parity_value))
        rx_error <= 1;
end

endmodule
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I don't see any particular problem with your code as illustrated. I would assume that either:

  • received_data has a 0 time glitch to a non-zero value at the clock edge. If you know how to enable delta cycles on your simulator you can investigate that. You have events firing. Are any of them affecting received_data?
  • If your simulator behaves like Martin's and treats ^(exp) as !(exp) then your simulator is buggy.

If you run this code the first three columns should be equal

module top;

reg [3:0] a;

initial begin
   for (int i = 0; i < 16; i++) begin
      a = i;
      $display("%0d %0d %0d %0d", a[3] ^ a[2] ^ a[1] ^ a[0], ^a, ^(a), !a);
   end
end

endmodule
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  • \$\begingroup\$ Ah. Sorry. Quickly reading the source code I read ^serial_in instead of ^received_data. \$\endgroup\$ – Martin Rosenau Dec 15 '17 at 14:42

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