As of now, I have been programming my Xilinx Spartan 6 using JTAG. I now want to load the FPGA image using SelectMap with my STM32 processor. (See this document (pages 33ff) for more information about SelectMap on the Spartan 6.)

At the moment I have a .bit file, and I'm loading one bit every clock cycle. I've been told that the .bit file may have to be converted to a .bin file somehow, and that the loading sequence should end with some "extra" clock cycles.

Neither of these points seems to be mentioned in the linked document. Should I convert my .bit file to a .bin file? Should I have "extra" clock cycles after loading the FPGA image?