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As of now, I have been programming my Xilinx Spartan 6 using JTAG. I now want to load the FPGA image using SelectMap with my STM32 processor. (See this document (pages 33ff) for more information about SelectMap on the Spartan 6.)

At the moment I have a .bit file, and I'm loading one bit every clock cycle. I've been told that the .bit file may have to be converted to a .bin file somehow, and that the loading sequence should end with some "extra" clock cycles.

Neither of these points seems to be mentioned in the linked document. Should I convert my .bit file to a .bin file? Should I have "extra" clock cycles after loading the FPGA image?

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You need the script bitformat.pl to convert bit to bin.

Select MAP is via a processor. You wish to look at XAPP502. In p. 4 is say you can use the .bit file if you skip the header. The bin file has no header information. Xilinx recommends .bin or .hex.

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    \$\begingroup\$ I've been parsing the bit files and using the single large data record's contents. Works great so far. The header info also helps me verify it is for the right device, etc. \$\endgroup\$
    – darron
    Jun 25, 2012 at 19:25
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You can tell bitgen to produce a .bin output instead of or as well at a .bit output. They are the same file, but the .bit one has a header on it.

In the old days, loading in some extra 0xFFs at the end of the real bitstream was found to be helpful, but I don't think it matters now.

[You can actually load the .bit file (using slave serial mode anyway) as the FPGA waits for a sync word (which is not part of the header) before it starts configuring.]

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