I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider code for the 7 seven of the basys3 by my instructor and I managed to do the stopwatch. When I changed all my constraints to the PMOD pins and connect to the external 7 segment I can see that it works because it stops and resets but it does the counting so quickly that I can't read at all.

I am thinking that the problem may be because of the clock divider and the frequency of the clocks. The given code states that since the original clock of the basys3 is 100 MHz a counter will count up to 500000 to obtain a 100 hz and another counter will count up to 208334 that is 240 Hz.

First of all I didn't understand why the second clock is 240 Hz and why do the counters count up to these irrelivant numbers. Secondly what can I do for the external 4 bit 7 segment to slow it down?

  • \$\begingroup\$ 240/4digit = 60Hz. So that's probably where that one comes from (60Hz refresh rate is quite standard). Beyond that it's hard to tell without context of where the clocks are used. \$\endgroup\$ – Tom Carpenter Dec 16 '17 at 22:37
  • \$\begingroup\$ 100MHz/208334 = 480Hz, so it will overflow 480 times per second, giving a clock rate (two overflows per clock to toggle a register) 240Hz - hence that number. \$\endgroup\$ – Tom Carpenter Dec 16 '17 at 22:39
  • \$\begingroup\$ First thing I ask all of my students is, do you have a block diagram? \$\endgroup\$ – zoder Dec 21 '17 at 7:50

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