# How do I design a PCB for high current applications?

I'm attempting to design a PCB that will have 8 high-side drivers. I'm struggling with designing the PCB, because it seems the pad on the back of chip isn't large enough to carry the max current it is rated for.

The FET is a VN7020AJTR. According to the data sheet, it's rated for 45 AMP maximum with internal current limiters. According to the PCB trace calculator I'm using, I'd need 32mil (or about .8mm) thick copper on the PCB to handle a trace that's only 2.2mm wide (the input pad on the FET is 2.2x2.9mm).

That's just at the FET. There will multiple FET, and we need to handle up to 100A total (we're limiting in software), I'd need traces 11mm wide.

The 100A limit is easy enough, I can supplement the current capacity by attaching a bus bar, but I still need the traces to handle the current to the pad.

I even considered putting the bus bar on the back side of the board and using multiple vias to transport the current to each pad. I haven't calculated how many vias I would need though. I'm sure it's several.

Now the question, Are my calculations correct? Do I need that much copper just to connect to the FET (assuming a copper bus bar is added) and how do I figure out how many vias I need if the bus bar is on the back side?

If this is anywhere near accurate, it might be better for me to split the FETS onto a separate board than the logic circuits.

• You can and should make the trace much wider than the PCB pad. For an application like this, the pad should be sitting in a giant copper fill area. You should also tweak your design to work with copper thicknesses you can readily get from PCB fab houses. Using wires or bus bars may be more economical than trying to run 100A on a PCB. That is a lot of current! Dec 17, 2017 at 6:23
• @mkeith I completely agree, however, the pad is on the bottom of a powerSSO-16 which has, so there are smaller pads on two sides of the package, so I can only reach the input pad from the bottom of the package, which leaves me coming in from the end or or through the PCB with a large number of vias. Dec 17, 2017 at 15:10
• I see. Well, you can still transition to wide copper as soon as you get away from the IC. Dec 17, 2017 at 18:12
• I was thinking of moving the high current bus to the back side of the board with vias. Dec 17, 2017 at 18:14
• I think it is OK to transition layers, but if the vias are outside of the pad, then you will have the same problem. I don't like to use pad-in-via designs, but it can be done. It is often done for large thermal pads. Dec 17, 2017 at 18:31

## Page 38 example R5 4L gives the lowest 'C/W rise.

It is impractical to choose copper tracks with 10 oz layers, so the prudent design uses heavy busbars as SIPs that carry high current. if low ESR and low ESL are critical then edge layout is mandatory with Litz wire interconnects with twist pair for lower EMI.

Busbars:
wave solderable edge conn.

more

• Stewart Please give more details on "edge layout". Are you talking about the radiative behaviors at edge of PCB? Dec 17, 2017 at 12:29
• Tony, I don't disagree, however the input pad is on the bottom of the package (2.2x2.9mm) with smaller pads on two sides, so I only have access to it from the ends of the package (on the 2.2mm edge) or by coming through the bottom of the PCB with a bunch of vias. Dec 17, 2017 at 15:12
• Busbars offer low ESR, stranded wire adds flex but Litz wire reduces ESL Dec 20, 2017 at 16:39
• Bus bars are probably a better choice but if you're really constrained on space and you have the money, some fabs can make 20,30,100oz and more traces. It's expensive though. epectec.com/articles/heavy-copper-pcb-design.html Not being contrarian, just adding to the discussion. Dec 20, 2017 at 17:19