I'm attempting to design a PCB that will have 8 high-side drivers. I'm struggling with designing the PCB, because it seems the pad on the back of chip isn't large enough to carry the max current it is rated for.
The FET is a VN7020AJTR. According to the data sheet, it's rated for 45 AMP maximum with internal current limiters. According to the PCB trace calculator I'm using, I'd need 32mil (or about .8mm) thick copper on the PCB to handle a trace that's only 2.2mm wide (the input pad on the FET is 2.2x2.9mm).
That's just at the FET. There will multiple FET, and we need to handle up to 100A total (we're limiting in software), I'd need traces 11mm wide.
The 100A limit is easy enough, I can supplement the current capacity by attaching a bus bar, but I still need the traces to handle the current to the pad.
I even considered putting the bus bar on the back side of the board and using multiple vias to transport the current to each pad. I haven't calculated how many vias I would need though. I'm sure it's several.
Now the question, Are my calculations correct? Do I need that much copper just to connect to the FET (assuming a copper bus bar is added) and how do I figure out how many vias I need if the bus bar is on the back side?
If this is anywhere near accurate, it might be better for me to split the FETS onto a separate board than the logic circuits.