# Why Non-parallel but full case statement uses ROM not the MUX?

as far as I know, when the items in case are not parallel

it would compose a priority routing network not the multiplexing network.

In other words, it should uses multiple 2-to-1 MUXs to represent priority in between the case items.

For example, below code has non-parallel case items 3'b11 and 3'b1??.

module non_parallel_but_full_case
(
input wire [2:0] s,
output reg y
);
always @*
//below case is not parallel but full case
casez (s)
3'b111: y = 1'b1;
3'b1??: y = 1'b0;
default: y = 1'b1;
endcase
endmodule


Therefore, I've expected the synthesized circuit may have MUXs not the ROM.

However, when I tested the code in the vivado and its RTL description shows ROM not the MUX.

Why the non-parallel case uses the ROM instead of the MUXs?

module decoder_2_4_if (
input wire [1:0] a,
input wire en,
output reg [3:0] y
);

always @*
if (en == 1'b0)
y = 4'b0000;
else if (a == 2'b00)
y = 4'b0001;
else if (a == 2'b01)
y = 4'b0010;
else if (a == 2'b10)
y = 4'b0100;
else
y = 4'b1000;
endmodule


The above code generates the multiple cascaded 2-to-1 MUXs.

However, the same logic implemented by the case statement uses the ROM.

module decoder_2_4_case (
input wire [1:0] a,
input wire en,
output reg [3:0] y
);

always @*
case ({en,a})
3'b000, 3'b001, 3'b010, 3'b011: y = 4'b000;
3'b100: y = 4'b0001;
3'b101: y = 4'b0010;
3'b110: y = 4'b0100;
3'b111: y = 4'b1000;
endcase
endmodule


In two examples, the result can be statically determined, and it would mean that two modules could be implemented by the ROM.

Then why it generates the different schematics?

Why the non-parallel case uses the ROM instead of the MUXs?

Because that's the right thing to do here!

You feed in values, you get out static values. Classical case for ROM, or in the case of FPGAs, an elemental LUT.

A mux would need the same LUT to mux the right static signals. So, the mux solution for this static case is less efficient than just ROM.

In other words, it should uses multiple 2-to-1 MUXs to represent priority in between the case items.

I don't see a reason why.

You implicitly define a priority order when doing your else if thing, so here, the synthesizer has no choice.
• you're mixing things up. It's not used because it's faster, it's used because any other implementation would include the same LUT component. and: < is an arithmetic operator. you need to implement arithmetic logic to have it. So, you tell me how the combinatorial way to compare two 64bit variables looks like, and then you see why we don't do that. Dec 17, 2017 at 13:08