I am designing a system with a carrier board that has all of active logic on one board and most connectors on a backplane board. The interface between the two boards is a x16 PCIe board edge connector. Over the edge connector I intend to route USB 3.1 (5 Gbit/s) from the source device (μPD720202) to a USB 3 A receptacle. On the carrier board the SSTX and SSRX lines are at most 30mm and length matched to less than 1mil. The USB traces are routed like PCIe signals would be on the edge connector: USB 3 connections over PCIe routing

  • \$\begingroup\$ What PCB material do you plan on using? \$\endgroup\$
    – pserra
    Dec 18, 2017 at 0:14
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    \$\begingroup\$ I am planning on using FR4, nothing exotic like rogers, I would guess that isn't specific enough but I don't know what types there are. \$\endgroup\$ Dec 19, 2017 at 0:17
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    \$\begingroup\$ As an update to this I did implement the design and it does work. Unfortunately I don't have any numbers that quantify the loss or signal integrity. The board with the μPD720202 has trace lengths between 0.25 and 0.5 inches and the backplane has trace lengths between 1 and 1.4 inches. \$\endgroup\$ Aug 21, 2018 at 18:37

1 Answer 1


You need to control the impedance of the whole signal path to 90 plus or minus 7 ohms. That includes the PCB trace, the receptical contact, the mating interface, the plug contact and the wire termination/PCB trace.

You also need to worry about insertion loss and differential insertion loss. (100 MHz, -1.5 dB; 1.25 GHz, -5.0 dB; 2.5 GHz, -7.5 dB; and 7.5 GHz, -25 dB).

It's not impossible but what often happens is that during the training phase of the USB the connection defaults to a USB 2 connection. The unreliability of system is frustrating and without a lot of expensive test kit it is not clear where the problem is and what to do about it.

Have a look at this paper: Managing Connector and Cable Assembly Performance for USB SuperSpeed amongst others at http://www.usb.org/developers/docs/whitepapers/


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