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In Common-Emitter amplifier the BE voltage is set near 0.7V but we apply both positive and negative swings to BJT and there is no distortion on output but the signal will be 0.7V+signal_value and 0.7V-signal_value. Why there is no distortion for 0.7V-signal_value? The BJT is not in conduting state now.

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  • \$\begingroup\$ there is no distortion Well actually there is. There is always some distortion as transistors are inherently non-linear devices. The question is, how much distortion is acceptable to you, for example you could set a limit of less than 1% distortion. With this circuit you'd need to use quite small signals (less than 100 mV) to get that. If you start seeing distortions of a sinewave then you're often already at more than 10% distortion. \$\endgroup\$ Dec 18, 2017 at 8:32
  • \$\begingroup\$ @Bimpelrekkie How the distorstions could be estimated during design process. How the acceptable distortions value may be included in calculations of an amplifier like previous? \$\endgroup\$
    – MaxMil
    Dec 18, 2017 at 8:34
  • \$\begingroup\$ I do that with "Fourier analysis" in the simulator. That shows me the frequency content of the signal. Say I feed a 1 kHz sinewave to the amp. The spectrum of that signal will be only one peak at 1 kHz. At the output peaks at multiples of 1 kHz will be present, 2 kHz, 3 kHz, etc... The 2 kHz is the second harmonic, 3 kHz is the third. If all peaks are 20 dB lower (a factor 10) than the 1 kHz peak my distortion is 10 %. -40 dB = 1 %. On a bench measuring the actual circuit I'd use a spectrum analyzer. \$\endgroup\$ Dec 18, 2017 at 8:39
  • \$\begingroup\$ Because the emitter voltage varies too, so Vbe remains (approx) 0.7V. \$\endgroup\$
    – user16324
    Dec 18, 2017 at 11:31
  • \$\begingroup\$ The voltage gain is a signal level dependent. Av = gm*Rc≈40*Ic * Rc. When the input signal swings positive so that the collector current increases, the voltage gain also increase his value. And for negative input signal swings the collector current drops. So the gain decreases his value. As you can see the voltage gain of this CE amplifier was changing together with Ic current. This represents a high level of distortion. \$\endgroup\$
    – G36
    Dec 18, 2017 at 15:50

2 Answers 2

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Your circuit is highly linearized by the 1.3 volts across the 500 ohm emitter resistor. Without that resistor (or if you boosted gain with 1,000uF in parallel with 500 ohms), you'd see serious distortion at 0.026 volts (major 2nd harmonic distortion), and about 10% distortion at 4 millivolts Peak-peak on the base.

The distortion is reduced by the ratio of 1.3/0.026 or 50:1.

Insert 4 volts peak-peak thru 1Kohm resistor (to protect the transistor) and you'll see distortion.

By the way, below 100Hz, you'll measure a dropoff in gain, because 1uF Cin implements HighPassFilter with Rin of your circuit.

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Regarding frequency respond, we'll consider the two nodes of the amplifier as having different frequency responses (thus different F3dB) because of the collector compliance (the stiffness of Icollector) does largely decouple the collector from the base.

Collector bandwidth will be 0.159 / (all resistors in parallel on collector * sum of all capacitors on the collector that are tied to GND). In this circuit, the resistors are 4K || 10K, or approx. 3K ohms. The capacitance is??? we'll assume 10pf (the 1uF does not tie to GND, so its not a parasitic capacitor). The time constant is 3K ohm * 10pF or 30 nanoseconds or 33MegaRadians/second. That divided by 2*pi == 5MHz F3dB (half power point, 40 degree phase shift).

Now for the input bandwidth. If you XFG1 has zero Zsource, the input bandwidth will be infinite (in reality, set by the base time constant: rbb' and Cemitter.) With finite Zsource, the amplifier's Cmiller will be a big bother. Assuming Cob is 10pF, and gain is 3Kohm / (500 + 26 ) ~~ 6x, the input capacitance will be 10pF * (1 + 6) = 70pF. If Zsource is 50 ohms, the 70pF * 50ohm = 3,500 nanoseconds or about 50MHz input bandwidth.

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  • \$\begingroup\$ To extent frequency bandwidth I need to use higher capacity not 1 but 100 uF and also I need to proper choo capacitor in parallel with 500 ohms?. Is there any practice article that you know (link) which can be used for bandwidth calculations? \$\endgroup\$
    – MaxMil
    Dec 18, 2017 at 17:55
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In your circuit, the biggest factor in play is R4, the emitter resistor. This provides negative feedback in the following way. As the signal rises, the collector current increases with it, and so does the emitter current. This causes a voltage drop across R4 which very nearly match the rise in base voltage, so V-BE doesn't rise much at all. There's also a corresponding reduction in gain because of this. The same thing happens when the signal goes negative, as long as the transistor was originally biased into conduction to start with.

I will also mention that a BJT is a current-operated device. As you try to raise the base voltage, it draws more current and the voltage doesn't rise by much. The signal voltage appears instead across the series base resistor...which you don't have. You do have C1, so this effect would be present at low frequencies. In real life, most circuits would have a series base resistor.

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